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Results:
1-7
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Results: 7
Authors:
PARK GH
KWON OY
HAN TD
KIM SD
YANG SB
Citation: Gh. Park et al., METHODS TO IMPROVE PERFORMANCE OF INSTRUCTION PREFETCHING THROUGH BALANCED IMPROVEMENT OF 2 PRIMARY PERFORMANCE-FACTORS, Journal of systems architecture, 44(9-10), 1998, pp. 755-772
Authors:
LEE NK
YANG SB
HAN TD
KIM SD
Citation: Nk. Lee et al., MODELING AND PERFORMANCE ANALYSIS OF DUAL HEAD DISK STRUCTURE, Journal of systems architecture, 44(9-10), 1998, pp. 787-802
Authors:
KIM Y
NOH MJ
HAN TD
KIM SD
Citation: Y. Kim et al., MAPPING OF NEURAL NETWORKS ONTO THE MEMORY-PROCESSOR INTEGRATED ARCHITECTURE, Neural networks, 11(6), 1998, pp. 1083-1098
Authors:
KIM JM
KIM Y
KIM SD
HAN TD
YANG SB
Citation: Jm. Kim et al., AN ADAPTIVE PARALLEL COMPUTER VISION SYSTEM, International journal of pattern recognition and artificial intelligence, 12(3), 1998, pp. 311-334
Authors:
KIM Y
KWON OY
HAN TD
MUN Y
Citation: Y. Kim et al., DESIGN AND PERFORMANCE ANALYSIS OF THE PRACTICAL FAT TREE NETWORK USING A BUTTERFLY NETWORK, Journal of systems architecture, 43(1-5), 1997, pp. 355-364
Authors:
PARK GH
KWON OY
HAN TD
KIM SD
Citation: Gh. Park et al., NON-REFERENCED PREFETCH (NRP) CACHE FOR INSTRUCTION PREFETCHING, IEE proceedings. Computers and digital techniques, 143(1), 1996, pp. 37-43
Authors:
PARK WC
LEE SW
KWON OY
HAN TD
KIM SD
Citation: Wc. Park et al., FLOATING-POINT ADDER SUBTRACTOR PERFORMING IEEE ROUNDING AND ADDITION/SUBTRACTION IN PARALLEL/, IEICE transactions on information and systems, E79D(4), 1996, pp. 297-305
Risultati:
1-7
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