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Results:
1-8
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Results: 8
Authors:
Segawa, H
Matsuura, Y
Kumaki, S
Matsumura, T
Scotzniovsky, S
Murayama, S
Wada, T
Harada, A
Ohara, E
Asano, K
Yoshida, T
Horiba, Y
Citation: H. Segawa et al., An embedded software scheme for a real-time single-chip MPEG-2 encoder system with a VLIW media processor core, IEICE TR EL, E84C(2), 2001, pp. 202-211
Authors:
Matsumura, T
Kumaki, S
Segawa, H
Ishihara, K
Hanami, A
Matsuura, Y
Scotzniovsky, S
Takata, H
Yamada, A
Murayama, S
Wada, T
Ohira, H
Shimada, T
Asano, K
Yoshida, T
Yoshimoto, M
Tsuchihashi, K
Horiba, Y
Citation: T. Matsumura et al., A single-chip MPEG-2 422P@ML video, audio, and system encoder with a 162 MHz media-processor core and dual motion estimation cores, IEICE TR EL, E84C(1), 2001, pp. 108-122
Authors:
Itoh, N
Naemura, Y
Makino, H
Nakase, Y
Yoshihara, T
Horiba, Y
Citation: N. Itoh et al., A 600-MHz 54x54-bit multiplier with rectangular-styled Wallace tree, IEEE J SOLI, 36(2), 2001, pp. 249-257
Authors:
Horiba, Y
Tsutsui, S
Citation: Y. Horiba et S. Tsutsui, International duopoly, tariff policy and the superiority of free trade, JPN ECON R, 51(2), 2000, pp. 207-220
Authors:
Ueda, K
Nii, K
Wada, Y
Maeda, S
Iwamatsu, T
Yamaguchi, Y
Ipposhi, T
Maegawa, S
Mashiko, K
Horiba, Y
Citation: K. Ueda et al., A CAD-compatible SOI-CMOS gate array using 0.35 mu m partially-depleted transistors, IEICE TR EL, E83C(2), 2000, pp. 205-211
Authors:
Komurasaki, H
Sato, H
Yamamoto, K
Ueda, K
Maeda, S
Yamaguchi, Y
Sasaki, N
Miki, T
Horiba, Y
Citation: H. Komurasaki et al., A sub 1-V L-band low noise amplifier in SOICMOS, IEICE T FUN, E83A(2), 2000, pp. 220-227
Authors:
Horiba, Y
Citation: Y. Horiba, Reader control in reading: Effects of language competence, text type, and task, DISCOURS PR, 29(3), 2000, pp. 223-267
Authors:
Takata, H
Watanabe, T
Nakajima, T
Takagaki, T
Sato, H
Mohri, A
Yamada, A
Kanamoto, T
Matsuda, Y
Iwade, S
Horiba, Y
Citation: H. Takata et al., The D30V/MPEG multimedia processor, IEEE MICRO, 19(4), 1999, pp. 38-47
Risultati:
1-8
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