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Results: 4

Authors: IGURA H NAITO Y KAZAMA K KURODA I MOTOMURA M YAMASHINA M
Citation: H. Igura et al., AN 800-MOPS, 110-MW, 1.5-V, PARALLEL DSP FOR MOBILE MULTIMEDIA PROCESSING, IEEE journal of solid-state circuits, 33(11), 1998, pp. 1820-1828

Authors: IZUMIKAWA M IGURA H FURUTA K ITO H WAKABAYASHI H NAKAJIMA K MOGAMI T HORIUCHI T YAMASHINA M
Citation: M. Izumikawa et al., A 0.25-MU-M CMOS-0.9 100-MHZ DSP CORE, IEEE journal of solid-state circuits, 32(1), 1997, pp. 52-61

Authors: MIZUNO M YAMASHINA M FURUTA K IGURA H ABIKO H OKABE K ONO A YAMADA H
Citation: M. Mizuno et al., A GHZ MOS ADAPTIVE PIPELINE TECHNIQUE USING MOS CURRENT-MODE LOGIC, IEEE journal of solid-state circuits, 31(6), 1996, pp. 784-791

Authors: SUZUKI K YAMASHINA M NAKAYAMA T IZUMIKAWA M NOMURA M IGURA H HEIUCHI H GOTO J INOUE T KOSEKI Y ABIKO H OKABE K ONO A YANO Y YAMADA H
Citation: K. Suzuki et al., A 500-MHZ, 32-BIT, 0.4-MU-M CMOS RISC PROCESSOR, IEEE journal of solid-state circuits, 29(12), 1994, pp. 1464-1473
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