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Results:
1-10
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Results: 10
Authors:
Lee, HY
Nam, KH
Yoon, JS
Han, JG
Jun, YH
Citation: Hy. Lee et al., Industrial application of WC-Ti(1-x)AlxN nanocomposite films synthesized by cathodic arc ion plating process on a printed circuit board drill, SURF COAT, 146, 2001, pp. 532-536
Authors:
Kong, BS
Kim, SS
Jun, YH
Citation: Bs. Kong et al., Conditional-capture flip-flop for statistical power reduction, IEEE J SOLI, 36(8), 2001, pp. 1263-1271
Authors:
Jang, SJ
Jun, YH
Lee, JG
Kong, BS
Citation: Sj. Jang et al., ASMD with duty cycle correction scheme for high-speed DRAM, ELECTR LETT, 37(16), 2001, pp. 1004-1006
Authors:
Lee, JG
Jun, YH
Lee, C
Kong, BS
Citation: Jg. Lee et al., I/O divided column redundancy scheme for high-speed DRAM with multiple I/Os, ELECTR LETT, 36(24), 2000, pp. 1996-1997
Authors:
Jeon, YW
Jun, YH
Kim, S
Citation: Yw. Jeon et al., Column redundancy scheme for multiple I/O DRAM using mapping table, ELECTR LETT, 36(11), 2000, pp. 940-942
Authors:
Kong, BS
Jun, YH
Citation: Bs. Kong et Yh. Jun, Set of self-timed latches for high-speed VLSI, IEE P-CIRC, 146(6), 1999, pp. 341-344
Authors:
Lee, JG
Jun, YH
Citation: Jg. Lee et Yh. Jun, A 1.6 gbyte/s 16-bank 72 Mb DRAM with block-decoded sub-YSEL driver, J KOR PHYS, 35, 1999, pp. S889-S892
Authors:
Kong, BS
Kang, DO
Jun, YH
Citation: Bs. Kong et al., A 1.5 V full-swing bootstrapped CMOS driver for low-voltage applications, J KOR PHYS, 35, 1999, pp. S983-S986
Authors:
Kong, BS
Jun, YH
Citation: Bs. Kong et Yh. Jun, Power-efficient low-voltage bootstrapped CMOS latched driver, ELECTR LETT, 35(24), 1999, pp. 2113-2115
Authors:
Jun, YH
Citation: Yh. Jun, Parallel logic simulation with assignable delays on a vector multiprocessor computer, IEE P-CIRC, 144(1), 1997, pp. 5-10
Risultati:
1-10
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