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Citation: M. Nakamura et al., A 29-NS 64-MB DRAM WITH HIERARCHICAL ARRAY ARCHITECTURE, IEEE journal of solid-state circuits, 31(9), 1996, pp. 1302-1307

Authors: KAWAHARA T KAWAJIRI Y HORIGUCHI M AKIBA T KITSUKAWA G KURE T AOKI M

Citation: T. Kawahara et al., A CHARGE RECYCLE REFRESH FOR GB-SCALE DRAMS IN FILE APPLICATIONS, IEEE journal of solid-state circuits, 29(6), 1994, pp. 715-722

Authors: KAWAHARA T SAKATA T ITOH K KAWAJIRI Y AKIBA T KITSUKAWA G AOKI M

Citation: T. Kawahara et al., A HIGH-SPEED, SMALL-AREA, THRESHOLD-VOLTAGE-MISMATCH COMPENSATION SENSE AMPLIFIER FOR GIGABIT-SCALE DRAM ARRAYS, IEEE journal of solid-state circuits, 28(7), 1993, pp. 816-823

Authors: KITSUKAWA G HORIGUCHI M KAWAJIRI Y KAWAHARA T AKIBA T KAWASE Y TACHIBANA T SAKAI T AOKI M SHUKURI S SAGARA K NAGAI R OHJI Y HASEGAWA N YOKOYAMA N KISU T YAMASHITA H KURE T NISHIDA T

Citation: G. Kitsukawa et al., 256-MB DRAM CIRCUIT TECHNOLOGIES FOR FILE APPLICATIONS, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1105-1113

Authors: KAWAHARA T HORIGUCHI M KAWAJIRI Y KITSUKAWA G KURE T AOKI M

Citation: T. Kawahara et al., SUBTHRESHOLD CURRENT REDUCTION FOR DECODED-DRIVER BY SELF-REVERSE BIASING, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1136-1144