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Results:
1-14
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Results: 14
Authors:
KUH ES
SANDBERG IW
Citation: Es. Kuh et Iw. Sandberg, IN-MEMORIAM - DARLINGTON,SIDNEY (JULY 18, 1906 0CTOBER 31, 1997), IEEE transactions on very large scale integration (VLSI) systems, 6(1), 1998, pp. 2-3
Authors:
KUH ES
SANDBERG IW
Citation: Es. Kuh et Iw. Sandberg, IN-MEMORIAM - DARLINGTON,SIDNEY (JULY 18, 1906 0CTOBER 31, 1997), IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(1), 1998, pp. 1-2
Authors:
KUH ES
SANDBERG IW
Citation: Es. Kuh et Iw. Sandberg, IN-MEMORIAM - DARLINGTON,SIDNEY (JULY 18, 1906 OCTOBER 31, 1997), IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 45(1), 1998, pp. 1-2
Authors:
KUH ES
SANDBERG IW
Citation: Es. Kuh et Iw. Sandberg, DARLINGTON,SIDNEY (JULY 18, 1906 0CTOBER 31, 1997) - IN-MEMORIAM, IEEE transactions on circuits and systems for video technology, 8(1), 1998, pp. 2-3
Authors:
PEDRAM M
BHAT N
KUH ES
Citation: M. Pedram et al., COMBINING TECHNOLOGY MAPPING WITH LAYOUT, VLSI design, 5(2), 1997, pp. 111-124
Authors:
MAO JF
KUH ES
Citation: Jf. Mao et Es. Kuh, FAST SIMULATION AND SENSITIVITY ANALYSIS OF LOSSY TRANSMISSION-LINES BY THE METHOD OF CHARACTERISTICS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 44(5), 1997, pp. 391-401
Authors:
XUE T
KUH ES
WANG DS
Citation: T. Xue et al., POST GLOBAL ROUTING CROSSTALK SYNTHESIS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(12), 1997, pp. 1418-1430
Authors:
HONG XL
XUE TX
HUANG J
CHENG CK
KUH ES
Citation: Xl. Hong et al., TIGER - AN EFFICIENT TIMING-DRIVEN GLOBAL ROUTER FOR GATE ARRAY AND STANDARD CELL LAYOUT DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 16(11), 1997, pp. 1323-1331
Authors:
KUH ES
SANDBERG IW
Citation: Es. Kuh et Iw. Sandberg, IN-MEMORIAM - DARLINGTON,SIDNEY (JULY 18, 1906 OCTOBER 31, 1997), IEEE transactions on computer-aided design of integrated circuits and systems, 16(10), 1997, pp. 1057-1058
Authors:
YU QJ
KUH ES
XUE TX
Citation: Qj. Yu et al., MOMENT MODELS OF GENERAL TRANSMISSION-LINES WITH APPLICATION TO INTERCONNECT ANALYSIS AND OPTIMIZATION, IEEE transactions on very large scale integration (VLSI) systems, 4(4), 1996, pp. 477-494
Authors:
YU QJ
KUH ES
Citation: Qj. Yu et Es. Kuh, AN ACCURATE TIME-DOMAIN INTERCONNECT MODEL OF TRANSMISSION-LINE NETWORKS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 43(3), 1996, pp. 200-208
Authors:
YU QJ
KUH ES
Citation: Qj. Yu et Es. Kuh, EXACT MOMENT MATCHING MODEL OF TRANSMISSION-LINES AND APPLICATION TO INTERCONNECT DELAY ESTIMATION, IEEE transactions on very large scale integration (VLSI) systems, 3(2), 1995, pp. 311-322
Authors:
ONOZAWA A
CHAUDHARY K
KUH ES
Citation: A. Onozawa et al., PERFORMANCE-DRIVEN SPACING ALGORITHMS USING ATTRACTIVE AND REPULSIVE CONSTRAINTS FOR SUBMICRON LSIS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(6), 1995, pp. 707-719
Authors:
LIN S
KUH ES
MAREKSADOWSKA M
Citation: S. Lin et al., STEPWISE EQUIVALENT CONDUCTANCE CIRCUIT SIMULATION TECHNIQUE, IEEE transactions on computer-aided design of integrated circuits and systems, 12(5), 1993, pp. 672-683
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1-14
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