AAAAAA

   
Results: 1-8 |
Results: 8
A new five-parameter MOS transistor mismatch model
Authors: Serrano-Gotarredona, T Linares-Barranco, B
Citation: T. Serrano-gotarredona et B. Linares-barranco, A new five-parameter MOS transistor mismatch model, IEEE ELEC D, 21(1), 2000, pp. 37-39
Adaptive Resonance Theory microchips
Authors: Serrano-Gotarredona, T Linares-Barranco, B
Citation: T. Serrano-gotarredona et B. Linares-barranco, Adaptive Resonance Theory microchips, STUD FUZZ S, 48, 2000, pp. 189-253
AER image filtering architecture for vision-processing systems
Authors: Serrano-Gotarredona, T Andreou, AG Linares-Barranco, B
Citation: T. Serrano-gotarredona et al., AER image filtering architecture for vision-processing systems, IEEE CIRC-I, 46(9), 1999, pp. 1064-1071
A general translinear principle for subthreshold MOS transistors
Authors: Serrano-Gotarredona, T Linares-Barranco, B Andreou, AG
Citation: T. Serrano-gotarredona et al., A general translinear principle for subthreshold MOS transistors, IEEE CIRC-I, 46(5), 1999, pp. 607-616
Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input
Authors: Serrano-Gotarredona, T Linares-Barranco, B Andreou, AG
Citation: T. Serrano-gotarredona et al., Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input, IEEE CIRC-I, 46(11), 1999, pp. 1398-1407
Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation
Authors: Serrano-Gotarredona, T Linares-Barranco, B
Citation: T. Serrano-gotarredona et B. Linares-barranco, Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation, ANALOG IN C, 21(3), 1999, pp. 271-296
Bipolar/CMOS current-source flip-flop for application in neuro-fuzzy systems
Authors: Serrano-Gotarredona, T Linares-Barranco, B Andreou, AG
Citation: T. Serrano-gotarredona et al., Bipolar/CMOS current-source flip-flop for application in neuro-fuzzy systems, ELECTR LETT, 35(16), 1999, pp. 1326-1328
ART1 and ARTMAP VLSI circuit implementation
Authors: Serrano-Gotarredona, T Linares-Barranco, B
Citation: T. Serrano-gotarredona et B. Linares-barranco, ART1 and ARTMAP VLSI circuit implementation, KLUW S ANAL, 512, 1999, pp. 163-191
Risultati: 1-8 |