Authors: TAUR Y MII YJ LOGAN R WONG HS

Citation: Y. Taur et al., ON EFFECTIVE CHANNEL-LENGTH IN O.1-MU-M MOSFETS, IEEE electron device letters, 16(4), 1995, pp. 136-138

Authors: EDELSTEIN DC SAIHALASZ GA MII YJ

Citation: Dc. Edelstein et al., VLSI ON-CHIP INTERCONNECTION PERFORMANCE SIMULATIONS AND MEASUREMENTS, IBM journal of research and development, 39(4), 1995, pp. 383-401

Authors: TAUR Y MII YJ FRANK DJ WONG HS BUCHANAN DA WIND SJ RISHTON SA SAIHALASZ GA NOWAK EJ

Citation: Y. Taur et al., CMOS SCALING INTO THE 21ST-CENTURY - 0.1-MU-M AND BEYOND, IBM journal of research and development, 39(1-2), 1995, pp. 245-260

Authors: RISHTON SA MII YJ KERN DP TAUR Y LEE KY LII T JENKINS K QUINLAN D BROWN T DANNER D SEWELL F POLCARI M

Citation: Sa. Rishton et al., HIGH-PERFORMANCE SUB-0.1 MU-M SILICON N-METAL OXIDE SEMICONDUCTOR TRANSISTORS WITH COMPOSITE METAL POLYSILICON GATES, Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 11(6), 1993, pp. 2612-2614

Authors: BURGHARTZ JN MII YJ

Citation: Jn. Burghartz et Yj. Mii, RELIABILITY IMPOSED DESIGN ASPECTS OF SUBMICROMETER POLYSILICON-EMITTER BIPOLAR-TRANSISTORS, IEEE electron device letters, 14(7), 1993, pp. 363-365

Authors: TAUR Y COHEN S WIND S LII T HSU C QUINLAN D CHANG CA BUCHANAN D AGNELLO P MII YJ REEVES C ACOVIC A KESAN V

Citation: Y. Taur et al., EXPERIMENTAL 0.1-MU-M P-CHANNEL MOSFET WITH P-POLYSILICON GATE ON 35-ANGSTROM GATE OXIDE(), IEEE electron device letters, 14(6), 1993, pp. 304-306