Authors: YAMANAKA H SAITO H KONDOH H SASAKI Y YAMADA H TSUZUKI M NISHIO S NOTANI H IWABU A ISHIWAKI M KOHAMA S MATSUDA Y OSHIMA K

Citation: H. Yamanaka et al., SCALABLE SHARED-BUFFERING ATM SWITCH WITH A VERSATILE SEARCHABLE QUEUE, IEEE journal on selected areas in communications, 15(5), 1997, pp. 773-784

Authors: YAMANAKA H SAITO H YAMADA H KONDOH H NOTANI H MATSUDA Y OSHIMA K

Citation: H. Yamanaka et al., SHARED MULTIBUFFER ATM SWITCHES WITH HIERARCHICAL QUEUING AND MULTICAST FUNCTIONS, IEICE transactions on communications, E79B(8), 1996, pp. 1109-1120

Authors: KONDOH H NOTANI H YOSHIMURA T SHIBATA H MATSUDA Y

Citation: H. Kondoh et al., A 1.5-V 250-MHZ TO 3.0-V 622-MHZ OPERATION CMOS PHASE-LOCKED LOOP WITH PRECHARGE TYPE PHASE-FREQUENCY DETECTOR, IEICE transactions on electronics, E78C(4), 1995, pp. 381-388

Authors: KONDOH H NOTANI H YAMANAKA H HIGASHITANI K SAITO H HAYASHI I MATSUDA Y OSHIMA K NAKAYA M

Citation: H. Kondoh et al., A SHARED MULTIBUFFER ARCHITECTURE FOR HIGH-SPEED ATM SWITCH LSIS, IEICE transactions on electronics, E76C(7), 1993, pp. 1094-1101

Authors: KONDOH H NOTANI H YAMANAKA H HIGASHITANI K SAITO H HAYASHI I KOHAMA S MATSUDA Y OSHIMA K NAKAYA M

Citation: H. Kondoh et al., A 622-MB S 8X8 ATM SWITCH CHIP SET WITH SHARED MULTIBUFFER ARCHITECTURE/, IEEE journal of solid-state circuits, 28(7), 1993, pp. 808-815

Authors: KONDOH H KOZAKI S MAKINO S NOTANI H HIDANI F NAKAYA M

Citation: H. Kondoh et al., A FULLY INTEGRATED 6.25-PERCENT PULL-IN RANGE DIGITAL PLL FOR ISDN PRIMARY RATE INTERFACE LSI, IEICE transactions on electronics, E75C(3), 1992, pp. 280-287