Authors:
Torres, J
Palleau, J
Tardiff, F
Bernard, H
Beverina, A
Motte, P
Pantel, R
Juhel, M
Citation: J. Torres et al., Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology, MICROEL ENG, 50(1-4), 2000, pp. 425-431
Authors:
Motte, P
Torres, J
Palleau, J
Tardif, F
Demolliens, O
Bernard, H
Citation: P. Motte et al., Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture, MICROEL ENG, 50(1-4), 2000, pp. 487-493
Authors:
Motte, P
Torres, J
Palleau, J
Tardif, F
Bernard, H
Citation: P. Motte et al., Study of Cu contamination during copper integration for subquarter micron technology, SOL ST ELEC, 43(6), 1999, pp. 1015-1018
Authors:
Ikeda, S
Palleau, J
Torres, J
Chenevier, B
Bourhila, N
Madar, R
Citation: S. Ikeda et al., TEM studies of the microstructure evolution in plasma treated CVD TiN thinfilms used as diffusion barriers, SOL ST ELEC, 43(6), 1999, pp. 1063-1068