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Results:
1-7
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Results: 7
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Dynamic state traversal for sequential circuit test generation, ACM T DES A, 5(3), 2000, pp. 548-565
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Peak power estimation of VLSI circuits: New peak power measures, IEEE VLSI, 8(4), 2000, pp. 435-439
Authors:
Hamzaoglu, I
Patel, JH
Citation: I. Hamzaoglu et Jh. Patel, Test set compaction algorithms for combinational circuits, IEEE COMP A, 19(8), 2000, pp. 957-963
Authors:
Hamzaoglu, I
Patel, JH
Citation: I. Hamzaoglu et Jh. Patel, New techniques for deterministic test pattern generation, J ELEC TEST, 15(1-2), 1999, pp. 63-73
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Fast static compaction algorithms for sequential circuit test vectors, IEEE COMPUT, 48(3), 1999, pp. 311-322
Authors:
Rudnick, EM
Patel, JH
Citation: Em. Rudnick et Jh. Patel, Efficient techniques for dynamic test sequence compaction, IEEE COMPUT, 48(3), 1999, pp. 323-330
Authors:
Hsu, FF
Patel, JH
Citation: Ff. Hsu et Jh. Patel, High-level controllability and observability analysis for test synthesis, J ELEC TEST, 13(2), 1998, pp. 93-103
Risultati:
1-7
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