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Citation: I. Polishchuk et al., Dual work function metal gate CMOS technology using metal interdiffusion, IEEE ELEC D, 22(9), 2001, pp. 444-446

Authors: Lu, Q Yeo, YC Yang, KJ Lin, R Polishchuk, I King, TJ Hu, CM Song, SC Luan, HF Kwong, DL Guo, X Luo, ZJ Wang, XW Ma, TP

Citation: Q. Lu et al., Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric, IEEE ELEC D, 22(7), 2001, pp. 324-326

Authors: Yeo, YC Lu, Q Ranade, P Takeuchi, H Yang, KJ Polishchuk, I King, TJ Hu, C Song, SC Luan, HF Kwong, DL

Citation: Yc. Yeo et al., Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric, IEEE ELEC D, 22(5), 2001, pp. 227-229

Authors: Polishchuk, I Burin, A Kagan, Y Maksimov, L

Citation: I. Polishchuk et al., Theory of relaxation phenomena in glasses and doped semiconductors at low temperatures, PHYSICA B, 280(1-4), 2000, pp. 253-257

Authors: Polishchuk, I Brown, G Huff, H

Citation: I. Polishchuk et al., Sources of resonance-related errors in capacitance versus voltage measurement systems, REV SCI INS, 71(10), 2000, pp. 3962-3963

Authors: Polishchuk, I Hu, CM

Citation: I. Polishchuk et Cm. Hu, Polycrystalline silicon/metal stacked gate for threshold voltage control in metal-oxide-semiconductor field-effect transistors, APPL PHYS L, 76(14), 2000, pp. 1938-1940