Authors: HWANG S RAJSUMAN R

Citation: S. Hwang et R. Rajsuman, VLSI TESTING FOR HIGH-RELIABILITY - MIXING I-DDQ TESTING WITH LOGIC TESTING, VLSI design, 5(3), 1997, pp. 299-311

Authors: ANDERSON TL CHANDRAMOULI R DEY S HEMMADY S MALLIPEDDI C RAJSUMAN R WALTHER R ZORIAN Y

Citation: Tl. Anderson et al., TESTING EMBEDDED CORES, IEEE design & test of computers, 14(2), 1997, pp. 81-89

Authors: MENON SM MALAIYA YK JAYASUMANA AP RAJSUMAN R

Citation: Sm. Menon et al., TESTABLE DESIGN OF BICMOS CIRCUITS FOR STUCK-OPEN FAULT-DETECTION USING SINGLE PATTERNS, IEEE journal of solid-state circuits, 30(8), 1995, pp. 855-863

Authors: VASKO DA RAJSUMAN R

Citation: Da. Vasko et R. Rajsuman, ANALYSIS AND SIMULATION OF MULTIPLE-RING TOKEN NETWORKS, IEE proceedings. Computers and digital techniques, 141(2), 1994, pp. 135-141

Authors: RAJSUMAN R

Citation: R. Rajsuman, A NEW TESTING METHOD FOR EEPLA, IEEE transactions on computer-aided design of integrated circuits and systems, 13(7), 1994, pp. 935-939