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Results:
1-8
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Results: 8
Authors:
MOURAD AN
FUCHS WK
SAAB DG
Citation: An. Mourad et al., SITE PARTITIONING FOR REDUNDANT ARRAYS OF DISTRIBUTED DISKS, Journal of parallel and distributed computing, 33(1), 1996, pp. 1-11
Authors:
SAAB DG
SAAB YG
ABRAHAM JA
Citation: Dg. Saab et al., AUTOMATIC TEST VECTOR CULTIVATION FOR SEQUENTIAL VLSI CIRCUITS USING GENETIC ALGORITHMS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(10), 1996, pp. 1278-1285
Authors:
CHEN CH
KARNIK T
SAAB DG
Citation: Ch. Chen et al., STRUCTURAL AND BEHAVIORAL SYNTHESIS FOR TESTABILITY TECHNIQUES, IEEE transactions on computer-aided design of integrated circuits and systems, 13(6), 1994, pp. 777-785
Authors:
NARAIN P
SAAB DG
KUNDA RP
ABRAHAM JA
Citation: P. Narain et al., A HIGH-LEVEL APPROACH TO TEST-GENERATION, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 40(7), 1993, pp. 483-492
Authors:
MUELLERTHUNS RB
SAAB DG
DAMIANO RF
ABRAHAM JA
Citation: Rb. Muellerthuns et al., BENCHMARKING PARALLEL-PROCESSING PLATFORMS - AN APPLICATIONS PERSPECTIVE, IEEE transactions on parallel and distributed systems, 4(8), 1993, pp. 947-954
Authors:
YANG AT
CHANG YH
SAAB DG
HAJJ IN
Citation: At. Yang et al., SWITCH-LEVEL TIMING SIMULATION OF BIPOLAR ECL CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(4), 1993, pp. 516-530
Authors:
MUELLERTHUNS RB
SAAB DG
DAMIANO RF
ABRAHAM JA
Citation: Rb. Muellerthuns et al., VLSI LOGIC AND FAULT SIMULATION ON GENERAL-PURPOSE PARALLEL COMPUTERS, IEEE transactions on computer-aided design of integrated circuits and systems, 12(3), 1993, pp. 446-460
Authors:
CHEN CH
SAAB DG
Citation: Ch. Chen et Dg. Saab, A NOVEL BEHAVIORAL TESTABILITY MEASURE, IEEE transactions on computer-aided design of integrated circuits and systems, 12(12), 1993, pp. 1960-1970
Risultati:
1-8
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