AAAAAA

   
Results: 1-10 |
Results: 10
COMPUTATION OF SWITCHING NOISE IN PRINTED-CIRCUIT BOARDS
Authors: YOOK JG CHANDRAMOULI V KATEHI LPB SAKALLAH KA ARABI TR SCHREYER TA
Citation: Jg. Yook et al., COMPUTATION OF SWITCHING NOISE IN PRINTED-CIRCUIT BOARDS, IEEE transactions on components, packaging, and manufacturing technology. Part A, 20(1), 1997, pp. 64-75
SELECTION OF VOLTAGE THRESHOLDS FOR DELAY MEASUREMENT
Authors: CHANDRAMOULI V SAKALLAH KA
Citation: V. Chandramouli et Ka. Sakallah, SELECTION OF VOLTAGE THRESHOLDS FOR DELAY MEASUREMENT, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 9-28
APPLICATION OF SYSTEM-LEVEL EM MODELING TO HIGH-SPEED DIGITAL IC PACKAGES AND PCBS
Authors: YOOK JG KATEHI LPB SAKALLAH KA MARTIN RS HUANG L SCHREYER TA
Citation: Jg. Yook et al., APPLICATION OF SYSTEM-LEVEL EM MODELING TO HIGH-SPEED DIGITAL IC PACKAGES AND PCBS, IEEE transactions on microwave theory and techniques, 45(10), 1997, pp. 1847-1856
RAVEL-XL - A HARDWARE ACCELERATOR FOR ASSIGNED-DELAY COMPILED-CODE LOGIC GATE SIMULATION
Authors: RIEPE MA MARQUES JP SAKALLAH KA BROWN RB
Citation: Ma. Riepe et al., RAVEL-XL - A HARDWARE ACCELERATOR FOR ASSIGNED-DELAY COMPILED-CODE LOGIC GATE SIMULATION, IEEE transactions on very large scale integration (VLSI) systems, 4(1), 1996, pp. 113-129
CRITICAL PATHS IN CIRCUITS WITH LEVEL-SENSITIVE LATCHES
Authors: BURKS TM SAKALLAH KA MUDGE TN
Citation: Tm. Burks et al., CRITICAL PATHS IN CIRCUITS WITH LEVEL-SENSITIVE LATCHES, IEEE transactions on very large scale integration (VLSI) systems, 3(2), 1995, pp. 273-291
TIMING MODELS FOR GALLIUM-ARSENIDE DIRECT-COUPLED FET LOGIC-CIRCUITS
Authors: KAYSSI AI SAKALLAH KA
Citation: Ai. Kayssi et Ka. Sakallah, TIMING MODELS FOR GALLIUM-ARSENIDE DIRECT-COUPLED FET LOGIC-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(3), 1995, pp. 384-393
MAXIMUM RATE SINGLE-PHASE CLOCKING OF A CLOSED PIPELINE INCLUDING WAVE PIPELINING, STOPPABILITY, AND STARTABILITY
Authors: CHANG CH DAVIDSON ES SAKALLAH KA
Citation: Ch. Chang et al., MAXIMUM RATE SINGLE-PHASE CLOCKING OF A CLOSED PIPELINE INCLUDING WAVE PIPELINING, STOPPABILITY, AND STARTABILITY, IEEE transactions on computer-aided design of integrated circuits and systems, 14(12), 1995, pp. 1526-1545
DELAY MACROMODELS FOR POINT-TO-POINT MCM INTERCONNECTIONS
Authors: KAYSSI AI SAKALLAH KA
Citation: Ai. Kayssi et Ka. Sakallah, DELAY MACROMODELS FOR POINT-TO-POINT MCM INTERCONNECTIONS, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 17(2), 1994, pp. 147-152
THE IMPACT OF SIGNAL TRANSITION TIME ON PATH DELAY COMPUTATION
Authors: KAYSSI AI SAKALLAH KA MUDGE TN
Citation: Ai. Kayssi et al., THE IMPACT OF SIGNAL TRANSITION TIME ON PATH DELAY COMPUTATION, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 40(5), 1993, pp. 302-309
SYNCHRONIZATION OF PIPELINES
Authors: SAKALLAH KA MUDGE TN BURKS TM DAVIDSON ES
Citation: Ka. Sakallah et al., SYNCHRONIZATION OF PIPELINES, IEEE transactions on computer-aided design of integrated circuits and systems, 12(8), 1993, pp. 1132-1146
Risultati: 1-10 |