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Results: 1-15 |
Results: 15
TRANSISTOR LEAKAGE FAULT-DIAGNOSIS FOR CMOS CIRCUITS
Authors: WEN XQ TAMAMOTO H SALUJA KK KINOSHITA K
Citation: Xq. Wen et al., TRANSISTOR LEAKAGE FAULT-DIAGNOSIS FOR CMOS CIRCUITS, IEICE transactions on information and systems, E81D(7), 1998, pp. 697-705
TRANSISTOR LEAKAGE FAULT-DIAGNOSIS WITH I-DDQ AND LOGIC INFORMATION
Authors: WEN XQ TAMAMOTO H SALUJA KK KINOSHITA K
Citation: Xq. Wen et al., TRANSISTOR LEAKAGE FAULT-DIAGNOSIS WITH I-DDQ AND LOGIC INFORMATION, IEICE transactions on information and systems, E81D(4), 1998, pp. 372-381
A NOVEL-APPROACH TO RANDOM PATTERN TESTING OF SEQUENTIAL-CIRCUITS
Authors: NACHMAN L SALUJA KK UPADHYAYA SJ REUSE R
Citation: L. Nachman et al., A NOVEL-APPROACH TO RANDOM PATTERN TESTING OF SEQUENTIAL-CIRCUITS, I.E.E.E. transactions on computers, 47(1), 1998, pp. 129-134
SCHEDULING TESTS FOR VLSI SYSTEMS UNDER POWER CONSTRAINTS
Authors: CHOU RM SALUJA KK AGRAWAL VD
Citation: Rm. Chou et al., SCHEDULING TESTS FOR VLSI SYSTEMS UNDER POWER CONSTRAINTS, IEEE transactions on very large scale integration (VLSI) systems, 5(2), 1997, pp. 175-185
SPECIAL ISSUE ON TEST SYNTHESIS - GUEST EDITORIAL
Authors: CHENG KT SALUJA KK WUNDERLICH HJ
Citation: Kt. Cheng et al., SPECIAL ISSUE ON TEST SYNTHESIS - GUEST EDITORIAL, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 11(1), 1997, pp. 7-8
HYSIM - HYBRID FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS
Authors: KIM K SALUJA KK
Citation: K. Kim et Kk. Saluja, HYSIM - HYBRID FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, VLSI design, 4(3), 1996, pp. 181-197
TESTING RECONFIGURED RAMS AND SCRAMBLED ADDRESS RAMS FOR PATTERN SENSITIVE FAULTS
Authors: FRANKLIN M SALUJA KK
Citation: M. Franklin et Kk. Saluja, TESTING RECONFIGURED RAMS AND SCRAMBLED ADDRESS RAMS FOR PATTERN SENSITIVE FAULTS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(9), 1996, pp. 1081-1087
TEST APPLICATION TIME REDUCTION FOR SEQUENTIAL-CIRCUITS WITH SCAN
Authors: LEE SY SALUJA KK
Citation: Sy. Lee et Kk. Saluja, TEST APPLICATION TIME REDUCTION FOR SEQUENTIAL-CIRCUITS WITH SCAN, IEEE transactions on computer-aided design of integrated circuits and systems, 14(9), 1995, pp. 1128-1140
ON-CHIP TESTING OF RANDOM-ACCESS MEMORIES
Authors: SALUJA KK
Citation: Kk. Saluja, ON-CHIP TESTING OF RANDOM-ACCESS MEMORIES, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 5(4), 1994, pp. 367-376
HYPERGRAPH COLORING AND RECONFIGURED RAM TESTING
Authors: FRANKLIN M SALUJA KK
Citation: M. Franklin et Kk. Saluja, HYPERGRAPH COLORING AND RECONFIGURED RAM TESTING, I.E.E.E. transactions on computers, 43(6), 1994, pp. 725-736
THEORY AND TECHNIQUES FOR TESTING CHECK BITS OF RAMS WITH ON-CHIP ECC
Authors: FRANKLIN M SALUJA KK
Citation: M. Franklin et Kk. Saluja, THEORY AND TECHNIQUES FOR TESTING CHECK BITS OF RAMS WITH ON-CHIP ECC, IEICE transactions on information and systems, E76D(10), 1993, pp. 1243-1252
A TUTORIAL ON BUILT-IN SELF-TEST .2. APPLICATIONS
Authors: AGRAWAL VD KIME CR SALUJA KK
Citation: Vd. Agrawal et al., A TUTORIAL ON BUILT-IN SELF-TEST .2. APPLICATIONS, IEEE design & test of computers, 10(2), 1993, pp. 69-77
AN EFFICIENT ALGORITHM FOR BIPARTITE PLA FOLDING
Authors: LIU CY SALUJA KK
Citation: Cy. Liu et Kk. Saluja, AN EFFICIENT ALGORITHM FOR BIPARTITE PLA FOLDING, IEEE transactions on computer-aided design of integrated circuits and systems, 12(12), 1993, pp. 1839-1847
TESTING CHECK BITS AT NO COST IN RAMS WITH ON-CHIP ECC
Authors: RAMANATHAN P SALUJA KK FRANKLIN M
Citation: P. Ramanathan et al., TESTING CHECK BITS AT NO COST IN RAMS WITH ON-CHIP ECC, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 304-312
AN EFFICIENT ALGORITHM FOR SEQUENTIAL-CIRCUIT TEST-GENERATION
Authors: KELSEY TP SALUJA KK LEE SY
Citation: Tp. Kelsey et al., AN EFFICIENT ALGORITHM FOR SEQUENTIAL-CIRCUIT TEST-GENERATION, I.E.E.E. transactions on computers, 42(11), 1993, pp. 1361-1371
Risultati: 1-15 |