Authors: Takeuchi, K Satoh, S Imamiya, K Sakui, K

Citation: K. Takeuchi et al., A source-line programming scheme for low-voltage operation NAND flash memories, IEEE J SOLI, 35(5), 2000, pp. 672-681

Authors: Banba, H Shiga, H Umezawa, A Miyaba, T Tanzawa, T Atsumi, S Sakui, K

Citation: H. Banba et al., A CMOS bandgap reference circuit with sub-1-V operation, IEEE J SOLI, 34(5), 1999, pp. 670-674

Authors: Takeuchi, K Satoh, S Tanaka, T Imamiya, K Sakui, K

Citation: K. Takeuchi et al., A negative V-th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories, IEEE J SOLI, 34(5), 1999, pp. 675-684

Authors: Imamiya, K Sugiura, Y Nakamura, H Himeno, T Takeuchi, K Ikehashi, T Kanda, K Hosono, K Shirota, R Aritome, S Shimizu, K Hatakeyama, K Sakui, K

Citation: K. Imamiya et al., A 130-mm(2), 256-mbit NAND flash with shallow trench isolation technology, IEEE J SOLI, 34(11), 1999, pp. 1536-1543