Authors: Solana, JM

Citation: Jm. Solana, Efficient test cost reduction procedure for parallel-serial scan circuits, ELECTR LETT, 37(21), 2001, pp. 1277-1278

Authors: Martin, O Solana, JM

Citation: O. Martin et Jm. Solana, Programmable processor for on-line computing of inverse Haar transform, ELECTR LETT, 37(16), 2001, pp. 1050-1052

Authors: Solana, JM Manzano, MA

Citation: Jm. Solana et Ma. Manzano, Limited maximum fault-multiplicity diagnosis procedure for scan designs, IEE P-COM D, 147(6), 2000, pp. 423-433

Authors: Solana, JM Manzano, MA

Citation: Jm. Solana et Ma. Manzano, PASE-scan design: A new full-scan structure to reduce test application time, IEE P-COM D, 146(6), 1999, pp. 283-293