Authors: YOSHIDA M HIRAMOTO T FUJIWARA T HASHIMOTO T MURAYA T MURATA S WATANABE K TAMBA N IKEDA T

Citation: M. Yoshida et al., A BIPOLAR-BASED 0.5 MU-M BICMOS TECHNOLOGY ON BONDED SOI FOR HIGH-SPEED LSIS, IEICE transactions on electronics, E77C(8), 1994, pp. 1395-1403

Authors: TAMBA N ANZAI A AKIMOTO K OHAYASHI M HIRAMOTO T KOKUBU T OHMORI S MURAYA T KISHIMOTO A TSUJI S HAYASHI H HANDA N IGARASHI T NAMBU H YOSHIDA M FUJIWARA T WATANABE K UCHIDA A ODAKA M YAMAGUCHI K IKEDA T

Citation: N. Tamba et al., A 1.5-NS 256-KB BICMOS SRAM WITH 60-PS 11-K LOGIC GATES, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1344-1352

Authors: TAMBA N ANZAI A AKIMOTO K OHAYASHI M HIRAMOTO T KOKUBU T OHMORI S MURAYA T KISHIMOTO A TSUJI S HAYASHI H HANDA N IGARASHI T NAMBU H YOSHIDA M FUJIWARA T WATANABE K UCHIDA A ODAKA M YAMAGUCHI K IKEDA T

Citation: N. Tamba et al., A 1.5-NS 256-KB BICMOS SRAM WITH 60-PS 11-K LOGIC GATES, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1344-1352

Authors: NAMBU H KANETANI K IDEI Y YAMAGUCHI K HIRAMOTO T TAMBA N WATANABE K ODAKA M IKEDA T OHHATA K SAKURAI Y HOMMA N

Citation: H. Nambu et al., REDUNDANCY TECHNIQUE FOR ULTRA-HIGH-SPEED STATIC RAMS, IEICE transactions on electronics, E76C(4), 1993, pp. 641-648

Authors: OHHATA K SAKURAI Y NAMBU H KANETANI K IDEI Y HIRAMOTO T TAMBA N YAMAGUCHI K ODAKA M WATANABE K IKEDA T HOMMA N

Citation: K. Ohhata et al., NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME, IEICE transactions on electronics, E76C(11), 1993, pp. 1611-1619