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Citation: T. Tanzawa et al., Wordline voltage generating system for low-power low-voltage flash memories, IEEE J SOLI, 36(1), 2001, pp. 55-63

Authors: Atsumi, S Umezawa, A Tanzawa, T Taura, T Shiga, H Takano, Y Miyaba, T Matsui, M Watanabe, H Isobe, K Kitamura, S Yamada, S Saito, M Mori, S Watanabe, T

Citation: S. Atsumi et al., A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme, IEEE J SOLI, 35(11), 2000, pp. 1648-1654

Authors: Tanzawa, T Takano, Y Taura, T Atsumi, S

Citation: T. Tanzawa et al., Design of a sense circuit for low-voltage flash memories, IEEE J SOLI, 35(10), 2000, pp. 1415-1421

Authors: Tanzawa, T Atsumi, S

Citation: T. Tanzawa et S. Atsumi, Optimization of word-line booster circuits for low-voltage flash memories, IEEE J SOLI, 34(8), 1999, pp. 1091-1098

Authors: Banba, H Shiga, H Umezawa, A Miyaba, T Tanzawa, T Atsumi, S Sakui, K

Citation: H. Banba et al., A CMOS bandgap reference circuit with sub-1-V operation, IEEE J SOLI, 34(5), 1999, pp. 670-674