Authors: Bakalis, D Kavousianos, X Vergos, HT Nikolos, D Alexiou, GP

Citation: D. Bakalis et al., Low power built-in self-test schemes for array and booth multipliers, VLSI DESIGN, 12(3), 2001, pp. 431-448

Authors: Vergos, HT Tsiatouhas, Y Haniotakis, T Nikolos, D Nicolaidis, M

Citation: Ht. Vergos et al., Path delay fault testing of multiplexer-based shifters, INT J ELECT, 88(8), 2001, pp. 923-937

Authors: Kalampoukas, L Nikolos, D Efstathiou, C Vergos, HT Kalamatianos, J

Citation: L. Kalampoukas et al., High-speed parallel-prefix module 2(n)-1 adders, IEEE COMPUT, 49(7), 2000, pp. 673-680

Authors: Nikolos, D Vergos, HT

Citation: D. Nikolos et Ht. Vergos, On the yield of VLSI processors with on-chip CPU cache, IEEE COMPUT, 48(10), 1999, pp. 1138-1144