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Results: 101-125/349
Authors:
COOK A
HUNT KJR
Citation: A. Cook et Kjr. Hunt, ARINC-653 - ACHIEVING SOFTWARE REUSE, Microprocessors and microsystems, 20(8), 1997, pp. 479-483
Authors:
PERKINS AE
BIRCH AD
DAVIES RCW
Citation: Ae. Perkins et al., SIMULATION OF FUTURE SYSTEM DATA-NETWORKS, Microprocessors and microsystems, 20(8), 1997, pp. 485-494
Authors:
PARKIN G
Citation: G. Parkin, COMPLEX-SYSTEMS PROVED AND IMPROVED, Microprocessors and microsystems, 20(8), 1997, pp. 495-499
Authors:
PILAUD D
Citation: D. Pilaud, EFFICIENT AUTOMATIC CODE GENERATION FOR EMBEDDED SYSTEMS, Microprocessors and microsystems, 20(8), 1997, pp. 501-504
Authors:
STEVEN G
CHRISTIANSON B
COLLINS R
POTTER R
STEVEN F
Citation: G. Steven et al., A SUPERSCALAR ARCHITECTURE TO EXPLOIT INSTRUCTION LEVEL PARALLELISM, Microprocessors and microsystems, 20(7), 1997, pp. 391-400
Authors:
KAGARIS D
Citation: D. Kagaris, A ROUTING ALGORITHM FOR ROW-BASED FPGAS, Microprocessors and microsystems, 20(7), 1997, pp. 401-407
Authors:
HENG ACK
LOW MYH
Citation: Ack. Heng et Myh. Low, LOOP PARALLELIZATION TOOL FOR MESSAGE-PASSING SYSTEMS, Microprocessors and microsystems, 20(7), 1997, pp. 409-421
Authors:
KWAI DM
PARHAMI B
Citation: Dm. Kwai et B. Parhami, AN ONLINE FAULT-DIAGNOSIS SCHEME FOR LINEAR PROCESSOR ARRAYS, Microprocessors and microsystems, 20(7), 1997, pp. 423-428
Authors:
LOW KS
LIM KW
RAHMAN MF
Citation: Ks. Low et al., A MICROPROCESSOR-BASED FULLY DIGITAL AC SERVO DRIVE, Microprocessors and microsystems, 20(7), 1997, pp. 429-436
Citation: SUPERVISOR ICS MONITOR BATTERY-POWERED EQUIPMENT (REPRINTED FROM MAXIM ENGINEERING JOURNAL), Microprocessors and microsystems, 20(7), 1997, pp. 437-442
Authors:
KEONG CC
YIN C
Citation: Cc. Keong et C. Yin, IMPLEMENTATION OF A DEDUCTIVE DATABASE SYSTEM USING SQLBASE, Microprocessors and microsystems, 20(6), 1997, pp. 317-323
Authors:
CHAN TS
GORTON I
Citation: Ts. Chan et I. Gorton, PARALLEL ARCHITECTURE SUPPORT FOR HIGH-SPEED PROTOCOL PROCESSING, Microprocessors and microsystems, 20(6), 1997, pp. 325-339
Authors:
PARTHIBAN R
RAVIKUMAR CP
KAKARALA R
SIVASWAMY J
Citation: R. Parthiban et al., PARALLELIZATION OF SYMMETRY DETECTION ALGORITHMS ON A NETWORK OF WORKSTATIONS, Microprocessors and microsystems, 20(6), 1997, pp. 341-349
Authors:
RAVIKUMAR C
PANDA CS
Citation: C. Ravikumar et Cs. Panda, ADAPTIVE ROUTING IN K-ARY N-CUBES USING INCOMPLETE DIAGNOSTIC INFORMATION, Microprocessors and microsystems, 20(6), 1997, pp. 351-360
Authors:
KIM T
KIM JM
MIN SL
KIM CS
MOO SM
HONG S
Citation: T. Kim et al., CACHE PERFORMANCE IMPROVEMENT THROUGH ON-DEMAND, IN-CACHE PAGE CLEARING, Microprocessors and microsystems, 20(6), 1997, pp. 361-371
Authors:
RAMAN S
REDDY NRK
Citation: S. Raman et Nrk. Reddy, A TRANSPUTER-BASED PARALLEL MACHINE TRANSLATION SYSTEM FOR INDIAN LANGUAGES, Microprocessors and microsystems, 20(6), 1997, pp. 373-383
Authors:
BOTSARIS PN
SPARIS PD
Citation: Pn. Botsaris et Pd. Sparis, MICROPROCESSOR-CONTROLLED 3-WAY CATALYST EFFICIENCY MONITORING-SYSTEM, Microprocessors and microsystems, 20(10), 1997, pp. 585-593
Authors:
KIM SW
KO H
HAHN WJ
HAHM JS
Citation: Sw. Kim et al., DESIGN AND IMPLEMENTATION OF DUAL PROCESSOR BLOCK WITH SHARED EXTERNAL CACHE MEMORY, Microprocessors and microsystems, 20(10), 1997, pp. 595-605
Authors:
ISOAHO J
KOPPA V
OKSALA J
OJALA P
Citation: J. Isoaho et al., BOAR - AN ADVANCED HW SW COEMULATION ENVIRONMENT FOR DSP SYSTEM-DEVELOPMENT/, Microprocessors and microsystems, 20(10), 1997, pp. 607-615
Authors:
GODENA G
Citation: G. Godena, CONCEPTUAL-MODEL FOR PROCESS-CONTROL SOFTWARE SPECIFICATION, Microprocessors and microsystems, 20(10), 1997, pp. 617-630
Authors:
LIOUPIS D
MILIOS S
Citation: D. Lioupis et S. Milios, EXPLORING CACHE PERFORMANCE IN MULTITHREADED PROCESSORS, Microprocessors and microsystems, 20(10), 1997, pp. 631-642
Authors:
KOKOLAKIS I
ANDREADIS I
TSALIDES P
Citation: I. Kokolakis et al., COMPARISON BETWEEN CELLULAR-AUTOMATA AND LINEAR FEEDBACK SHIFT REGISTERS BASED PSEUDORANDOM NUMBER GENERATORS, Microprocessors and microsystems, 20(10), 1997, pp. 643-658
Authors:
VEGLIS AA
POMBORTSIS AS
Citation: Aa. Veglis et As. Pombortsis, PERFORMANCE ANALYSIS OF CLOS INTERCONNECTION NETWORKS UNDER NONUNIFORM TRAFFIC PATTERNS, Microprocessors and microsystems, 20(5), 1996, pp. 261-265
Authors:
KLAPURI H
HAMALAINEN T
SAARINEN J
KASKI K
Citation: H. Klapuri et al., MAPPING ARTIFICIAL NEURAL NETWORKS TO A TREE SHAPE NEUROCOMPUTER, Microprocessors and microsystems, 20(5), 1996, pp. 267-276
Authors:
FORSELL MJ
Citation: Mj. Forsell, MINIMAL PIPELINE ARCHITECTURE - AN ALTERNATIVE TO SUPERSCALAR ARCHITECTURE, Microprocessors and microsystems, 20(5), 1996, pp. 277-284