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Table of contents of journal: *VLSI design (Print)

Results: 26-50/339
Special issue - Low power architecture and circuit design: Computer aided design - Preface
Authors: Cho, JD
Citation: Jd. Cho, Special issue - Low power architecture and circuit design: Computer aided design - Preface, VLSI DESIGN, 12(2), 2001, pp. I-III
Deep-submicron placement minimizing crosstalk
Authors: Cho, JD Cho, JY
Citation: Jd. Cho et Jy. Cho, Deep-submicron placement minimizing crosstalk, VLSI DESIGN, 12(1), 2001, pp. 1-12
Two-dimensional placement using tabu search
Authors: Emmert, JM Bhatia, DK
Citation: Jm. Emmert et Dk. Bhatia, Two-dimensional placement using tabu search, VLSI DESIGN, 12(1), 2001, pp. 13-23
A universal, dynamically adaptable and programmable network router for parallel computers
Authors: Golota, TI Ziavras, SG
Citation: Ti. Golota et Sg. Ziavras, A universal, dynamically adaptable and programmable network router for parallel computers, VLSI DESIGN, 12(1), 2001, pp. 25-52
A fast algorithm for transistor folding
Authors: Cheng, EYC Sahni, S
Citation: Eyc. Cheng et S. Sahni, A fast algorithm for transistor folding, VLSI DESIGN, 12(1), 2001, pp. 53-60
A size-optimization design for variable length coding using distributed logic
Authors: Hsia, SC Tseng, CC
Citation: Sc. Hsia et Cc. Tseng, A size-optimization design for variable length coding using distributed logic, VLSI DESIGN, 12(1), 2001, pp. 61-68
A probabilistic power estimation method for combinational circuits under real gate delay model (Reprinted from Proceedings of 1999 IEEE InternationalSymposium on Circuits and Systems (ICAS), May 30-June 2, 1999, Orlando, Floria, USA, vol 1, pg 286-289, 1999)
Authors: Theodoridis, G Theoharis, S Soudris, D Goutis, C
Citation: G. Theodoridis et al., A probabilistic power estimation method for combinational circuits under real gate delay model (Reprinted from Proceedings of 1999 IEEE InternationalSymposium on Circuits and Systems (ICAS), May 30-June 2, 1999, Orlando, Floria, USA, vol 1, pg 286-289, 1999), VLSI DESIGN, 12(1), 2001, pp. 69-79
Distributed fault simulation algorithms on parallel virtual machine
Authors: Ravikumar, CP Jain, V Dod, A
Citation: Cp. Ravikumar et al., Distributed fault simulation algorithms on parallel virtual machine, VLSI DESIGN, 12(1), 2001, pp. 81-99
Minimization of k-variable-mixed-polarity Reed-Muller expansions
Authors: Falkowski, BJ Chang, CH
Citation: Bj. Falkowski et Ch. Chang, Minimization of k-variable-mixed-polarity Reed-Muller expansions, VLSI DESIGN, 11(4), 2000, pp. 311-320
Design of MOS-translinear multiplier/dividers in analog VLSI
Authors: Lopez-Martin, AJ Carlosena, A
Citation: Aj. Lopez-martin et A. Carlosena, Design of MOS-translinear multiplier/dividers in analog VLSI, VLSI DESIGN, 11(4), 2000, pp. 321-329
Design and analysis of radix-8/4/2 64b/32b integer divider using COMPASS cell library
Authors: Wang, CC Huang, CJ Chang, IY
Citation: Cc. Wang et al., Design and analysis of radix-8/4/2 64b/32b integer divider using COMPASS cell library, VLSI DESIGN, 11(4), 2000, pp. 331-338
A new bus assignment algorithm for a shared bus switch fabric
Authors: Torres, D Gonzalez, J Guzman, M
Citation: D. Torres et al., A new bus assignment algorithm for a shared bus switch fabric, VLSI DESIGN, 11(4), 2000, pp. 339-351
Design and analysis of digital ratioed compressors for inner product processing
Authors: Wang, CC Huang, CJ Lee, PM
Citation: Cc. Wang et al., Design and analysis of digital ratioed compressors for inner product processing, VLSI DESIGN, 11(4), 2000, pp. 353-361
Graphical design techniques for fixed-point multiplication
Authors: Dempster, AG
Citation: Ag. Dempster, Graphical design techniques for fixed-point multiplication, VLSI DESIGN, 11(4), 2000, pp. 363-379
An integrated approach to data path synthesis for behavioral-level power optimization
Authors: Park, C Kim, T Liu, CL
Citation: C. Park et al., An integrated approach to data path synthesis for behavioral-level power optimization, VLSI DESIGN, 11(4), 2000, pp. 381-396
Low power VLSI implementation of the DCT on single multiplier DSP processors
Authors: Masupe, S Arslan, T
Citation: S. Masupe et T. Arslan, Low power VLSI implementation of the DCT on single multiplier DSP processors, VLSI DESIGN, 11(4), 2000, pp. 397-403
A chip for a routing table based on a novel modified trie algorithm
Authors: Torres, D Larios, A Guzman, M
Citation: D. Torres et al., A chip for a routing table based on a novel modified trie algorithm, VLSI DESIGN, 11(4), 2000, pp. 405-415
Tutorial on VLSI partitioning
Authors: Chen, SJ Cheng, CK
Citation: Sj. Chen et Ck. Cheng, Tutorial on VLSI partitioning, VLSI DESIGN, 11(3), 2000, pp. 175-218
FPGA partitioning with complex resource constraints
Authors: Liu, HQ Zhu, K Wong, DF
Citation: Hq. Liu et al., FPGA partitioning with complex resource constraints, VLSI DESIGN, 11(3), 2000, pp. 219-235
Circuit partitioning for FPGAs by the Optimal Circuit Reduction Method
Authors: Bazylevych, RP Melnyk, RA Rybak, OG
Citation: Rp. Bazylevych et al., Circuit partitioning for FPGAs by the Optimal Circuit Reduction Method, VLSI DESIGN, 11(3), 2000, pp. 237-248
Iterative partitioning with varying node weights
Authors: Caldwell, AE Kahng, AB Markov, IL
Citation: Ae. Caldwell et al., Iterative partitioning with varying node weights, VLSI DESIGN, 11(3), 2000, pp. 249-258
Tabu Search: A meta heuristic for netlist partitioning
Authors: Areibi, S Vannelli, A
Citation: S. Areibi et A. Vannelli, Tabu Search: A meta heuristic for netlist partitioning, VLSI DESIGN, 11(3), 2000, pp. 259-283
Multilevel k-way hypergraph partitioning
Authors: Karypis, G Kumar, V
Citation: G. Karypis et V. Kumar, Multilevel k-way hypergraph partitioning, VLSI DESIGN, 11(3), 2000, pp. 285-300
A new 2-way multi-level partitioning algorithm
Authors: Saab, Y
Citation: Y. Saab, A new 2-way multi-level partitioning algorithm, VLSI DESIGN, 11(3), 2000, pp. 301-310
Untitled
Authors: Saab, Y
Citation: Y. Saab, Untitled, VLSI DESIGN, 11(3), 2000, pp. I-I
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