Citation: J. Cong et Yy. Hwang, Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping, IEEE COMP A, 20(9), 2001, pp. 1077-1090
Citation: J. Cong et Yy. Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM T DES A, 5(2), 2000, pp. 193-225
Citation: Cc. Chang et J. Cong, An efficient approach to multilayer layer assignment with an application to via minimization, IEEE COMP A, 18(5), 1999, pp. 608-620
Citation: J. Cong et L. He, Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing, IEEE COMP A, 18(4), 1999, pp. 406-420