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Results:
1-11
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Results: 11
Authors:
Cong, J
Hwang, YY
Citation: J. Cong et Yy. Hwang, Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping, IEEE COMP A, 20(9), 2001, pp. 1077-1090
Authors:
Cong, J
He, L
Koh, CK
Pan, Z
Citation: J. Cong et al., Interconnect sizing and spacing with consideration of coupling capacitance, IEEE COMP A, 20(9), 2001, pp. 1164-1169
Authors:
Cong, J
Pan, Z
Citation: J. Cong et Z. Pan, Interconnect performance estimation models for design planning, IEEE COMP A, 20(6), 2001, pp. 739-752
Authors:
Chang, CC
Cong, J
Citation: Cc. Chang et J. Cong, Pseudopin assignment with crosstalk noise control, IEEE COMP A, 20(5), 2001, pp. 598-611
Authors:
Cong, J
Koh, CK
Madden, PH
Citation: J. Cong et al., Interconnect layout optimization under higher order RLC model for MCM designs, IEEE COMP A, 20(12), 2001, pp. 1455-1463
Authors:
Cong, J
Citation: J. Cong, An interconnect-centric design flow for nanometer technologies, P IEEE, 89(4), 2001, pp. 505-528
Authors:
Cong, J
Hwang, YY
Citation: J. Cong et Yy. Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM T DES A, 5(2), 2000, pp. 193-225
Authors:
Cong, J
Fang, J
Khoo, KY
Citation: J. Cong et al., Via design rule consideration in multilayer maze routing algorithms, IEEE COMP A, 19(2), 2000, pp. 215-223
Authors:
Chang, CC
Cong, J
Citation: Cc. Chang et J. Cong, An efficient approach to multilayer layer assignment with an application to via minimization, IEEE COMP A, 18(5), 1999, pp. 608-620
Authors:
Cong, J
He, L
Citation: J. Cong et L. He, Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing, IEEE COMP A, 18(4), 1999, pp. 406-420
Authors:
Cong, J
Wu, C
Citation: J. Cong et C. Wu, Optimal FPGA mapping and retiming with efficient initial state computation, IEEE COMP A, 18(11), 1999, pp. 1595-1607
Risultati:
1-11
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