AAAAAA

   
Results: 1-5 |
Results: 5

Authors: Peralias, EJ Rueda, A Huertas, JL
Citation: Ej. Peralias et al., New BIST schemes for structural testing of pipelined analog to digital converters, J ELEC TEST, 17(5), 2001, pp. 373-383

Authors: Quintana, JM Avedillo, MJ Huertas, JL
Citation: Jm. Quintana et al., Efficient realization of a threshold voter for self-purging redundancy, J ELEC TEST, 17(1), 2001, pp. 69-73

Authors: Bellido-Diaz, MJ Juan-Chico, J Acosta, AJ Valencia, M Huertas, JL
Citation: Mj. Bellido-diaz et al., Logical modelling of delay degradation effect in static CMOS gates, IEE P-CIRC, 147(2), 2000, pp. 107-117

Authors: Baturone, I Sanchez-Solano, S Huertas, JL
Citation: I. Baturone et al., CMOS design of a current-mode multiplier/divider circuit with applicationsto fuzzy controllers, ANALOG IN C, 23(3), 2000, pp. 199-210

Authors: Garcia, TA Acosta, AJ Mora, JM Ramos, J Huertas, JL
Citation: Ta. Garcia et al., Self-timed boundary-scan cells for multi-chip module test, J ELEC TEST, 15(1-2), 1999, pp. 115-127
Risultati: 1-5 |