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Results: 1-7 |
Results: 7
Charge-sharing alleviation and detection for CMOS domino circuits
Authors: Chang, SC Cheng, CH Jone, WB Lee, SD Wang, JS
Citation: Sc. Chang et al., Charge-sharing alleviation and detection for CMOS domino circuits, IEEE COMP A, 20(2), 2001, pp. 266-280
An adaptive path selection method for delay testing
Authors: Jone, WB Yeh, WS Yeh, CW Das, SR
Citation: Wb. Jone et al., An adaptive path selection method for delay testing, IEEE INSTR, 50(5), 2001, pp. 1109-1118
Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
Authors: Rau, JC Jone, WB Chang, SC Wu, YL
Citation: Jc. Rau et al., Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits, IEE P-COM D, 147(5), 2000, pp. 343-348
Reducing test application time by scan flip-flops sharing
Authors: Chan, SC Lee, KJ Wu, ZZ Jone, WB
Citation: Sc. Chan et al., Reducing test application time by scan flip-flops sharing, IEE P-COM D, 147(1), 2000, pp. 42-48
TAIR: Testability analysis by implication reasoning
Authors: Chang, SC Jone, WB Chang, SS
Citation: Sc. Chang et al., TAIR: Testability analysis by implication reasoning, IEEE COMP A, 19(1), 2000, pp. 152-160
Low-speed scan testing of charge-sharing faults for CMOS domino circuits
Authors: Cheng, CH Jone, WB Chang, SC Wang, JS
Citation: Ch. Cheng et al., Low-speed scan testing of charge-sharing faults for CMOS domino circuits, ELECTR LETT, 36(20), 2000, pp. 1684-1685
Segmented bus design for low-power systems
Authors: Chen, JY Jone, WB Wang, JS Lu, HI Chen, TF
Citation: Jy. Chen et al., Segmented bus design for low-power systems, IEEE VLSI, 7(1), 1999, pp. 25-29
Risultati: 1-7 |