Authors: Kishine, K Ishihara, N Ichino, H

Citation: K. Kishine et al., Techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs - Duplicated loop control CDR, IEICE TR EL, E84C(4), 2001, pp. 460-469

Authors: Ishii, K Kishine, K Ichino, H

Citation: K. Ishii et al., A jitter suppression technique for a clock multiplier, IEICE TR EL, E83C(4), 2000, pp. 647-651

Authors: Hirose, M Kishine, K Ichino, H Ishihara, N

Citation: M. Hirose et al., Low-power 2.5-Gb/s Si-bipolar IC chipset for optical receivers and transmitters using low-voltage and adjustment-free circuit techniques, IEICE TR EL, E82C(3), 1999, pp. 511-518

Authors: Kishine, K Ishihara, N Takiguchi, K Ichino, H

Citation: K. Kishine et al., A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN'S and WAN's, IEEE J SOLI, 34(6), 1999, pp. 805-812

Authors: Kishine, K Takiguchi, K Ichino, H

Citation: K. Kishine et al., 2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique, ELECTR LETT, 35(5), 1999, pp. 360-361