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Results: 1-6 |
Results: 6

Authors: Kuo, DS Wang, C Chu, S Liang, MS Tsai, CS Tao, HJ Huang, YC Wu, JR Chen, YT Chih, YD Hsieh, CH Sung, HC Yeh, JK Lin, CJ Wong, SC Lin, SH Hsieh, CT Chu, WT Chen, HP Hsu, C Shyu, DS Peng, SP Fong, TJ Lee, KY
Citation: Ds. Kuo et al., A flash-based SOC technology using a split-gate cell, MICROEL ENG, 59(1-4), 2001, pp. 203-211

Authors: Huang, KC Fang, YK Yaung, DN Chen, CH Hsu, YL Ting, SF Lin, Y Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., A novel programming technique for highly scalable and disturbance immune flash EEPROM, SOL ST ELEC, 45(2), 2001, pp. 297-301

Authors: Liew, BK Wang, CC Diaz, CH Wu, SY Sun, JYC Lin, YF Kuo, DS Lin, HT Yen, A
Citation: Bk. Liew et al., Application of technology CAD in process development for high performance logic and system-on-chip in IC foundry, IEICE TR EL, E83C(8), 2000, pp. 1275-1280

Authors: Huang, KC Fang, YK Yaung, DN Chen, CW Sung, HC Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., The impacts of control gate voltage on the cycling endurance of split gateflash memory, IEEE ELEC D, 21(7), 2000, pp. 359-361

Authors: Huang, KC Fang, YK Yaung, DN Chen, CW Sung, HC Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory, IEEE ELEC D, 20(8), 1999, pp. 412-414

Authors: Huang, KC Fang, YK Yaung, DN Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., Improved programming performance of EEPROM/flash cell using post-poly-Si gate N2O annealing, ELECTR LETT, 35(13), 1999, pp. 1112-1114
Risultati: 1-6 |