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Results: 1-8 |
Results: 8
A formal approach to context scheduling for multicontext reconfigurable architectures
Authors: Maestre, R Kurdahi, FJ Fernandez, M Hermida, R Bagherzadeh, N Singh, H
Citation: R. Maestre et al., A formal approach to context scheduling for multicontext reconfigurable architectures, IEEE VLSI, 9(1), 2001, pp. 173-185
Design and implementation of the MorphoSys reconfigurable computing processor
Authors: Lee, MH Singh, H Lu, GM Bagherzadeh, N Kurdahi, FJ Eliseu, MC Alves, VC
Citation: Mh. Lee et al., Design and implementation of the MorphoSys reconfigurable computing processor, J VLSI S P, 24(2-3), 2000, pp. 147-164
Guest editors' introduction: Configurable computing
Authors: Kurdahi, FJ Bagherzadeh, N Athanas, P Munoz, JL
Citation: Fj. Kurdahi et al., Guest editors' introduction: Configurable computing, IEEE DES T, 17(1), 2000, pp. 17-19
MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
Authors: Singh, H Lee, MH Lu, GM Kurdahi, FJ Bagherzadeh, N Chaves, EM
Citation: H. Singh et al., MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications, IEEE COMPUT, 49(5), 2000, pp. 465-481
System-level time-stationary control synthesis for pipelined data paths (vol 9, pg 159, 1999)
Authors: Kim, JT Kurdahi, FJ Park, NB
Citation: Jt. Kim et al., System-level time-stationary control synthesis for pipelined data paths (vol 9, pg 159, 1999), VLSI DESIGN, 9(4), 1999, pp. NIL_1-NIL_1
System-level time-stationary control synthesis for pipelined data paths
Authors: Kim, JT Kurdahi, FJ Park, NB
Citation: Jt. Kim et al., System-level time-stationary control synthesis for pipelined data paths, VLSI DESIGN, 9(2), 1999, pp. 159-180
High-level synthesis of recoverable VLSI microarchitectures
Authors: Blough, DM Kurdahi, FJ Ohm, SY
Citation: Dm. Blough et al., High-level synthesis of recoverable VLSI microarchitectures, IEEE VLSI, 7(4), 1999, pp. 401-410
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGA's
Authors: Xu, M Kurdahi, FJ
Citation: M. Xu et Fj. Kurdahi, Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGA's, IEEE VLSI, 7(4), 1999, pp. 411-418
Risultati: 1-8 |