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Results:
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Results: 22
Authors:
ENDOH T
SHINMEI K
SAKURABA H
MASUOKA F
Citation: T. Endoh et al., THE ANALYSIS OF THE STACKED SURROUNDING GATE TRANSISTOR (S-SGT) DRAM FOR THE HIGH-SPEED AND LOW-VOLTAGE OPERATION, IEICE transactions on electronics, E81C(9), 1998, pp. 1491-1498
Authors:
ENDOH T
NAKAMURA K
MASUOKA F
Citation: T. Endoh et al., EVALUATION OF THE VOLTAGE DOWN-CONVERTER (VDC) WITH LOW RATIO OF CONSUMING CURRENT TO LOAD CURRENT IN DC AC OPERATION MODE/, IEICE transactions on electronics, E81C(6), 1998, pp. 968-974
Authors:
ENDOH T
SHIMIZU K
IIZUKA H
MASUOKA F
Citation: T. Endoh et al., A NEW WRITE ERASE METHOD TO IMPROVE THE READ DISTURB CHARACTERISTICS BASED ON THE DECAY PHENOMENA OF STRESS LEAKAGE CURRENT FOR MASH MEMORIES/, I.E.E.E. transactions on electron devices, 45(1), 1998, pp. 98-104
Authors:
ENDOH T
MASUOKA F
Citation: T. Endoh et F. Masuoka, ENDURANCE CHARACTERISTICS OF FLASH EEPROMS, Electronics & communications in Japan. Part 2, Electronics, 80(1), 1997, pp. 88-95
Authors:
MASUOKA F
Citation: F. Masuoka, SPECIAL ISSUE ON NEW CONCEPT DEVICE AND NOVEL ARCHITECTURE LSIS, IEICE transactions on electronics, E80C(7), 1997, pp. 839-840
Authors:
ENDOH T
NAKAMURA T
MASUOKA F
Citation: T. Endoh et al., AN ACCURATE MODEL OF FULLY-DEPLETED SURROUNDING GATE TRANSISTOR (FD-SGT), IEICE transactions on electronics, E80C(7), 1997, pp. 905-910
Authors:
ENDOH T
NAKAMURA T
MASUOKA F
Citation: T. Endoh et al., AN ANALYTIC STEADY-STATE CURRENT-VOLTAGE CHARACTERISTICS OF SHORT-CHANNEL FULLY-DEPLETED SURROUNDING GATE TRANSISTOR (FD-SGT), IEICE transactions on electronics, E80C(7), 1997, pp. 911-917
Authors:
ENDOH T
SHIMIZU K
IIZUKA H
MASUOKA F
Citation: T. Endoh et al., NEW REDUCTION-MECHANISM OF THE STRESS LEAKAGE CURRENT BASED ON THE DEACTIVATION OF STEP TUNNELING SITES FOR THIN OXIDE-FILMS, IEICE transactions on electronics, E80C(10), 1997, pp. 1310-1316
Authors:
ENDOH T
IIZUKA H
SHIROTA R
MASUOKA F
Citation: T. Endoh et al., NEW WRITE ERASE OPERATION TECHNOLOGY FOR FLASH EEPROM CELLS TO IMPROVE THE READ DISTURB CHARACTERISTICS/, IEICE transactions on electronics, E80C(10), 1997, pp. 1317-1323
Authors:
IIZUKA H
ENDOH T
ARITOME S
SHIROTA R
MASUOKA F
Citation: H. Iizuka et al., A NOVEL PROGRAMMING METHOD USING A REVERSE POLARITY PULSE IN FLASH EEPROMS, IEICE transactions on electronics, E79C(6), 1996, pp. 832-835
Authors:
MASUOKA F
Citation: F. Masuoka, FOREWORD, Sharp giho, (64), 1996, pp. 3-4
Authors:
NISHIZAWA JI
TAKEDA N
MASUOKA F
Citation: Ji. Nishizawa et al., CHARACTERISTICS OF SILICON N(-N(-)-N(+) DIODE WITH SUBMICROMETER N(-)REGION()), I.E.E.E. transactions on electron devices, 43(12), 1996, pp. 2068-2073
Authors:
OOWAKI Y
MABUCHI K
WATANABE S
OHUCHI K
MATSUNAGA J
MASUOKA F
Citation: Y. Oowaki et al., NEW ALPHA-PARTICLE INDUCED SOFT ERROR MECHANISM IN A 3-DIMENSIONAL CAPACITOR CELL, IEICE transactions on electronics, E78C(7), 1995, pp. 845-851
Authors:
WATANABE S
TSUCHIDA K
TAKASHIMA D
OOWAKI Y
NITAYAMA A
HIEDA K
TAKATO H
SUNOUCHI K
HORIGUCHI F
OHUCHI K
MASUOKA F
HARA H
Citation: S. Watanabe et al., A NOVEL CIRCUIT TECHNOLOGY WITH SURROUNDING GATE TRANSISTORS (SGTS) FOR ULTRA-HIGH DENSITY DRAMS, IEEE journal of solid-state circuits, 30(9), 1995, pp. 960-971
Authors:
YAMASHITA H
SASAKI M
OHSAWA S
MIYAGAWA R
OHBA E
MABUCHI K
NAKAMURA N
TANAKA N
ENDOH N
INOUE I
MATSUNAGA Y
EGAWA Y
ENDO Y
YAMAGUCHI T
IIDA Y
FURUKAWA A
MANABE S
ISHIZUKA Y
ICHINOSE H
NIIYAMA T
IHARA H
NOZAKI H
YANASE I
SAKUMA N
SAKAKUBO T
HONDA H
MASUOKA F
YOSHIDA O
TANGO H
SANO S
Citation: H. Yamashita et al., A 2 3-IN 2-MILLION PIXEL STACK-CCD HDTV IMAGER/, IEEE journal of solid-state circuits, 30(8), 1995, pp. 881-889
Authors:
MASUOKA F
Citation: F. Masuoka, SPECIAL SECTION ON HIGH-SPEED AND HIGH-DENSITY MULTIFUNCTIONAL LSI MEMORIES - FOREWORD, IEICE transactions on electronics, E77C(8), 1994, pp. 1249-1250
Authors:
SAKUI K
MASUOKA F
Citation: K. Sakui et F. Masuoka, SUB-HALFMICRON FLASH MEMORY TECHNOLOGIES, IEICE transactions on electronics, E77C(8), 1994, pp. 1251-1259
Authors:
ARITOME S
SHIROTA R
SAKUI K
MASUOKA F
Citation: S. Aritome et al., DATA RETENTION CHARACTERISTICS OF FLASH MEMORY CELLS AFTER WRITE AND ERASE CYCLING, IEICE transactions on electronics, E77C(8), 1994, pp. 1287-1295
Authors:
TANAKA T
TANAKA Y
NAKAMURA H
SAKUI K
OODAIRA H
SHIROTA R
OHUCHI K
MASUOKA F
HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373
Authors:
TANAKA T
TANAKA Y
NAKAMURA H
SAKUI K
OODAIRA H
SHIROTA R
OHUCHI K
MASUOKA F
HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373
Authors:
ARITOME S
SHIROTA R
HEMINK G
ENDOH T
MASUOKA F
Citation: S. Aritome et al., RELIABILITY ISSUES OF FLASH MEMORY CELLS, Proceedings of the IEEE, 81(5), 1993, pp. 776-788
Authors:
HASEGAWA T
TAKASHIMA D
OGIWARA R
OHTA M
SHIRATAKE S
HAMAMOTO T
YAMADA T
AOKI M
ISHIBASHI S
OOWAKI Y
WATANABE S
MASUOKA F
Citation: T. Hasegawa et al., AN EXPERIMENTAL DRAM WITH A NAND-STRUCTURED CELL, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1099-1104
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