Authors:
SAEKI T
NAKAOKA Y
FUJITA M
TANAKA A
NAGATA K
SAKAKIBARA K
MATANO T
HOSHINO Y
MIYANO K
ISA S
NAKAZAWA S
KAKEHASHI E
DRYNAN JM
KOMURO M
FUKASE T
IWASAKI H
TAKENAKA M
SEKINE J
IGETA M
NAKANISHI N
ITANI T
YOSHIDA K
YOSHINO H
HASHIMOTO S
YOSHII T
ICHINOSE M
IMURA T
UZIIE M
KIKUCHI S
KOYAMA K
FUKUZO Y
OKUDA T
Citation: T. Saeki et al., A 2.5-NS CLOCK ACCESS, 250-MHZ, 256-MB SDRAM WITH SYNCHRONOUS MIRROR DELAY, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1656-1668