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Citation: F. Murabayashi et al., 2.5 V CMOS CIRCUIT TECHNIQUES FOR A 200 MHZ SUPERSCALAR RISC PROCESSOR, IEEE journal of solid-state circuits, 31(7), 1996, pp. 972-980

Authors: TANAKA S HOTTA T MURABAYASHI F YAMADA H YOSHIDA S SHIMAMURA K KATSURA K BANDOH T IKEDA K MATSUBARA K SAITOU K NAKANO T SHIMIZU T SATOMURA R

Citation: S. Tanaka et al., A 120-MHZ BICMOS SUPERSCALAR RISC PROCESSOR, IEICE transactions on electronics, E77C(5), 1994, pp. 719-726

Authors: TANAKA S HOTTA T MURABAYASHI F YAMADA H YOSHIDA S SHIMAMURA K KATSURA K BANDOH T IKEDA K MATSUBARA K SAITOU K NAKANO T SHIMIZU T SATOMURA R

Citation: S. Tanaka et al., A 120-MHZ BICMOS SUPERSCALAR RISC PROCESSOR, IEEE journal of solid-state circuits, 29(4), 1994, pp. 389-396

Authors: MURABAYASHI F HOTTA T TANAKA S YAMAUCHI T YAMADA H NAKANO T KOBAYASHI Y BANDOH T

Citation: F. Murabayashi et al., 3.3V BICMOS CIRCUIT TECHNIQUES FOR A 120MHZ RISC MICROPROCESSOR, IEEE journal of solid-state circuits, 29(3), 1994, pp. 298-302

Authors: MURABAYASHI F YAMAUCHI T IWAMURA M HOTTA T NAKANO T KOBAYASHI Y

Citation: F. Murabayashi et al., BICMOS CIRCUIT TECHNIQUES FOR 3.3-V MICROPROCESSORS, IEICE transactions on electronics, E76C(5), 1993, pp. 695-700