Authors: NARITAKE I SUGIBAYASHI T UTSUGI S MUROTANI T

Citation: I. Naritake et al., A CROSSING CHARGE RECYCLE REFRESH SCHEME WITH A SEPARATED DRIVER SENSE-AMPLIFIER FOR GB DRAMS, IEICE transactions on electronics, E79C(6), 1996, pp. 787-791

Authors: SUGIBAYASHI T NARITAKE I UTSUGI S SHIBAHARA K OIKAWA R MORI H IWAO S MUROTANI T KOYAMA K FUKUZAWA S ITANI T KASAMA K OKUDA T OHYA S OGAWA M

Citation: T. Sugibayashi et al., A 1-GB DRAM FOR FILE APPLICATIONS, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1277-1280

Authors: SUGIBAYASHI T NARITAKE I TAKADA H INOUE K YAMAMOTO I MATANO T FUJITA M AIMOTO Y TAKESHIMA T UTSUGI S

Citation: T. Sugibayashi et al., A DISTRIBUTIVE SERIAL MULTIBIT PARALLEL TEST SCHEME FOR LARGE-CAPACITY DRAMS, IEICE transactions on electronics, E77C(8), 1994, pp. 1323-1327

Authors: SUGIBAYASHI T TAKESHIMA T NARITAKE I MATANO T TAKADA H AIMOTO Y FURUTA K FUJITA M SAEKI T SUGAWARA H MUROTANI T KASAI N SHIBAHARA K NAKAJIMA K HADA H HAMADA T AIZAKI N KUNIO T KAKEHASHI E MASUMORI K TANIGAWA T

Citation: T. Sugibayashi et al., A 30-NS 256-MB DRAM WITH A MULTIDIVIDED ARRAY STRUCTURE, IEEE journal of solid-state circuits, 28(11), 1993, pp. 1092-1098