Citation: N. Park et Kk. O, Body bias dependence of 1/f noise in NMOS transistors from deep-subthreshold to strong inversion, IEEE DEVICE, 48(5), 2001, pp. 999-1001
Citation: Jt. Colvin et al., Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology, IEEE J SOLI, 34(9), 1999, pp. 1339-1344
Citation: Hy. Yan et al., A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)(2)) latch and its application in a dual-modulus prescaler, IEEE J SOLI, 34(10), 1999, pp. 1400-1404
Authors:
Ho, YC
Kim, KH
Floyd, BA
Wann, C
Taur, Y
Lagnado, I
O, KK
Citation: Yc. Ho et al., 4- and 13-GHz tuned amplifiers implemented in a 0.1-mu m CMOS technology on SOI, SOS, and bulk substrates, IEEE J SOLI, 33(12), 1998, pp. 2066-2073