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Results: 1-17 |
Results: 17
HIGH-PERFORMANCE OF SILICIDED SILICON-SIDEWALL SOURCE AND DRAIN ((SD)-D-4) STRUCTURE
Authors: YOSHITOMI T SAITO M OHGURO T ONO M MOMOSE HS MORIFUJI E MORIMOTO T KATSUMATA Y IWAI H
Citation: T. Yoshitomi et al., HIGH-PERFORMANCE OF SILICIDED SILICON-SIDEWALL SOURCE AND DRAIN ((SD)-D-4) STRUCTURE, I.E.E.E. transactions on electron devices, 45(6), 1998, pp. 1295-1299
STUDY OF THE MANUFACTURING FEASIBILITY OF 1.5-NM DIRECT-TUNNELING GATE OXIDE MOSFETS - UNIFORMITY, RELIABILITY, AND DOPANT PENETRATION OF THE GATE OXIDE
Authors: MOMOSE HS NAKAMURA S OHGURO T YOSHITOMI T MORIFUJI E MORIMOTO T KATSUMATA Y IWAI H
Citation: Hs. Momose et al., STUDY OF THE MANUFACTURING FEASIBILITY OF 1.5-NM DIRECT-TUNNELING GATE OXIDE MOSFETS - UNIFORMITY, RELIABILITY, AND DOPANT PENETRATION OF THE GATE OXIDE, I.E.E.E. transactions on electron devices, 45(3), 1998, pp. 691-700
UNDOPED EPITAXIAL SI CHANNEL N-MOSFET GROWN BY UHV-CVD WITH PREHEATING
Authors: OHGURO T SUGIYAMA N IMAI S USUDA K SAITO M YOSHITOMI T ONO M KIMIJIMA H MOMOSE HS KATSUMATA Y IWAI H
Citation: T. Ohguro et al., UNDOPED EPITAXIAL SI CHANNEL N-MOSFET GROWN BY UHV-CVD WITH PREHEATING, I.E.E.E. transactions on electron devices, 45(3), 1998, pp. 710-716
0.15-MU-M BURIED-CHANNEL P-MOSFETS WITH ULTRATHIN BORON-DOPED EPITAXIAL SI LAYER
Authors: OHGURO T YAMADA K SUGIYAMA N IMAI S USUDA K YOSHITOMI T FIEGNA C ONO M SAITO M MOMOSE HS KATSUMATA Y IWAI H
Citation: T. Ohguro et al., 0.15-MU-M BURIED-CHANNEL P-MOSFETS WITH ULTRATHIN BORON-DOPED EPITAXIAL SI LAYER, I.E.E.E. transactions on electron devices, 45(3), 1998, pp. 717-721
0.15-MU-M RF CMOS TECHNOLOGY COMPATIBLE WITH LOGIC CMOS FOR LOW-VOLTAGE OPERATION
Authors: SAITO M ONO M FUJIMOTO R TANIMOTO H ITO N YOSHITOMI T OHGURO T MOMOSE HS IWAI H
Citation: M. Saito et al., 0.15-MU-M RF CMOS TECHNOLOGY COMPATIBLE WITH LOGIC CMOS FOR LOW-VOLTAGE OPERATION, I.E.E.E. transactions on electron devices, 45(3), 1998, pp. 737-742
THE IMPACT OF SCALING DOWN TO DEEP-SUBMICRON ON CMOS RF CIRCUITS
Authors: HUANG QT PIAZZA F ORSATTI P OHGURO T
Citation: Qt. Huang et al., THE IMPACT OF SCALING DOWN TO DEEP-SUBMICRON ON CMOS RF CIRCUITS, IEEE journal of solid-state circuits, 33(7), 1998, pp. 1023-1036
THE CLOSURE CLASS OF MIN SIGMA(0) IS NPO-PB
Authors: OHGURO T
Citation: T. Ohguro, THE CLOSURE CLASS OF MIN SIGMA(0) IS NPO-PB, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(1), 1997, pp. 242-246
PROSPECTS FOR LOW-POWER, HIGH-SPEED MPUS USING 1.5 NM DIRECT-TUNNELING GATE OXIDE MOSFET
Authors: MOMOSE HS ONO M YOSHITOMI T OHGURO T NAKAMURA SI SAITO M IWAI H
Citation: Hs. Momose et al., PROSPECTS FOR LOW-POWER, HIGH-SPEED MPUS USING 1.5 NM DIRECT-TUNNELING GATE OXIDE MOSFET, Solid-state electronics, 41(5), 1997, pp. 707-714
A HOT-CARRIER DEGRADATION MECHANISM AND ELECTRICAL CHARACTERISTICS IN(SD)-D-4 N-MOSFETS
Authors: YOSHITOMI T SAITO M OHGURO T ONO M MOMOSE HS MORIFUJI E MORIMOTO T KATSUMATA Y IWAI H
Citation: T. Yoshitomi et al., A HOT-CARRIER DEGRADATION MECHANISM AND ELECTRICAL CHARACTERISTICS IN(SD)-D-4 N-MOSFETS, I.E.E.E. transactions on electron devices, 44(11), 1997, pp. 2053-2058
REALIZATION OF HIGH-PERFORMANCE MOSFETS WITH GATE LENGTHS OF 0.1 MU-MOR LESS
Authors: MOMOSE HS ONO M YOSHITOMI T OHGURO T SAITO M IWAI H NAKAMURA S
Citation: Hs. Momose et al., REALIZATION OF HIGH-PERFORMANCE MOSFETS WITH GATE LENGTHS OF 0.1 MU-MOR LESS, Electronics & communications in Japan. Part 2, Electronics, 79(10), 1996, pp. 67-78
1.5 NM DIRECT-TUNNELING GATE OXIDE SI MOSFETS
Authors: MOMOSE HS ONO M YOSHITOMI T OHGURO T NAKAMURA S SAITO M IWAI H
Citation: Hs. Momose et al., 1.5 NM DIRECT-TUNNELING GATE OXIDE SI MOSFETS, I.E.E.E. transactions on electron devices, 43(8), 1996, pp. 1233-1242
FABRICATION OF SUB-50-NM GATE LENGTH N-METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS AND THEIR ELECTRICAL CHARACTERISTICS
Authors: ONO M SAITO M YOSHITOMI T FIEGNA C OHGURO T MOMOSE HS IWAI H
Citation: M. Ono et al., FABRICATION OF SUB-50-NM GATE LENGTH N-METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS AND THEIR ELECTRICAL CHARACTERISTICS, Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 13(4), 1995, pp. 1740-1743
RELATIONSHIP OF LOW-DENSITY-LIPOPROTEIN PARTICLE-SIZE TO PLASMA-LIPOPROTEINS, OBESITY, AND INSULIN-RESISTANCE IN JAPANESE MEN
Authors: SUEHIRO T OHGURO T SUMIYOSHI R YASUOKA N NAKAUCHI Y KUMON Y HASHIMOTO K
Citation: T. Suehiro et al., RELATIONSHIP OF LOW-DENSITY-LIPOPROTEIN PARTICLE-SIZE TO PLASMA-LIPOPROTEINS, OBESITY, AND INSULIN-RESISTANCE IN JAPANESE MEN, Diabetes care, 18(3), 1995, pp. 333-338
A STUDY ON HOT-CARRIER EFFECTS ON N-MOSFETS UNDER HIGH SUBSTRATE IMPURITY CONCENTRATION
Authors: ONO M SAITO M YOSHITOMI T FIEGNA C OHGURO T MOMOSE HS IWAI H
Citation: M. Ono et al., A STUDY ON HOT-CARRIER EFFECTS ON N-MOSFETS UNDER HIGH SUBSTRATE IMPURITY CONCENTRATION, I.E.E.E. transactions on electron devices, 42(8), 1995, pp. 1510-1521
SELF-ALIGNED NICKEL-MONO-SILICIDE TECHNOLOGY FOR HIGH-SPEED DEEP-SUBMICROMETER LOGIC CMOS ULSI
Authors: MORIMOTO T OHGURO T MOMOSE HS IINUMA T KUNISHIMA I SUGURO K KATAKABE I NAKAJIMA H TSUCHIAKI M ONO M KATSUMATA Y IWAI H
Citation: T. Morimoto et al., SELF-ALIGNED NICKEL-MONO-SILICIDE TECHNOLOGY FOR HIGH-SPEED DEEP-SUBMICROMETER LOGIC CMOS ULSI, I.E.E.E. transactions on electron devices, 42(5), 1995, pp. 915-922
A 40 NM GATE LENGTH N-MOSFET
Authors: ONO M SAITO M YOSHITOMI T FIEGNA C OHGURO T IWAI H
Citation: M. Ono et al., A 40 NM GATE LENGTH N-MOSFET, I.E.E.E. transactions on electron devices, 42(10), 1995, pp. 1822-1830
ANALYSIS OF RESISTANCE BEHAVIOR IN TI-SALICIDED AND NI-SALICIDED POLYSILICON FILMS
Authors: OHGURO T NAKAMURA S KOIKE M MORIMOTO T NISHIYAMA A USHIKU Y YOSHITOMI T ONO M SAITO M IWAI H
Citation: T. Ohguro et al., ANALYSIS OF RESISTANCE BEHAVIOR IN TI-SALICIDED AND NI-SALICIDED POLYSILICON FILMS, I.E.E.E. transactions on electron devices, 41(12), 1994, pp. 2305-2317
Risultati: 1-17 |