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Results: 1-25 | 26-28
Results: 1-25/28
CYCLE-ACCURATE MACRO-MODELS FOR RT-LEVEL POWER ANALYSIS
Authors: WU Q QIU Q PEDRAM M DING CS
Citation: Q. Wu et al., CYCLE-ACCURATE MACRO-MODELS FOR RT-LEVEL POWER ANALYSIS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 520-528
STRATIFIED RANDOM SAMPLING FOR POWER ESTIMATION
Authors: DING CS WU Q HSIEH CT PEDRAM M
Citation: Cs. Ding et al., STRATIFIED RANDOM SAMPLING FOR POWER ESTIMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 17(6), 1998, pp. 465-471
PROBABILISTIC MODELING OF DEPENDENCIES DURING SWITCHING ACTIVITY ANALYSIS
Authors: MARCULESCU R MARCULESCU D PEDRAM M
Citation: R. Marculescu et al., PROBABILISTIC MODELING OF DEPENDENCIES DURING SWITCHING ACTIVITY ANALYSIS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(2), 1998, pp. 73-83
ACCURATE AND EFFICIENT POWER SIMULATION STRATEGY BY COMPACTING THE INPUT VECTOR SET
Authors: TSUI CY PEDRAM M
Citation: Cy. Tsui et M. Pedram, ACCURATE AND EFFICIENT POWER SIMULATION STRATEGY BY COMPACTING THE INPUT VECTOR SET, Integration, 25(1), 1998, pp. 37-52
POWER OPTIMIZATION IN VLSI LAYOUT - A SURVEY
Authors: PEDRAM M VAISHNAV H
Citation: M. Pedram et H. Vaishnav, POWER OPTIMIZATION IN VLSI LAYOUT - A SURVEY, Journal of VLSI signal processing systems for signal, image, and video technology, 15(3), 1997, pp. 221-232
COMBINING TECHNOLOGY MAPPING WITH LAYOUT
Authors: PEDRAM M BHAT N KUH ES
Citation: M. Pedram et al., COMBINING TECHNOLOGY MAPPING WITH LAYOUT, VLSI design, 5(2), 1997, pp. 111-124
SPECIAL ISSUE ON LOW-POWER ELECTRONICS AND DESIGN
Authors: BARTON B PEDRAM M
Citation: B. Barton et M. Pedram, SPECIAL ISSUE ON LOW-POWER ELECTRONICS AND DESIGN, IEEE transactions on very large scale integration (VLSI) systems, 5(4), 1997, pp. 349-351
ENERGY MINIMIZATION USING MULTIPLE SUPPLY VOLTAGES
Authors: CHANG JM PEDRAM M
Citation: Jm. Chang et M. Pedram, ENERGY MINIMIZATION USING MULTIPLE SUPPLY VOLTAGES, IEEE transactions on very large scale integration (VLSI) systems, 5(4), 1997, pp. 436-443
A NEW DESCRIPTION OF MOS CIRCUITS AT SWITCH-LEVEL WITH APPLICATIONS
Authors: PEDRAM M WU XW
Citation: M. Pedram et Xw. Wu, A NEW DESCRIPTION OF MOS CIRCUITS AT SWITCH-LEVEL WITH APPLICATIONS, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1892-1901
VECTOR COMPACTION USING DYNAMIC MARKOV-MODELS
Authors: MARCULESCU R MARCULESCU D PEDRAM M
Citation: R. Marculescu et al., VECTOR COMPACTION USING DYNAMIC MARKOV-MODELS, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1924-1933
STATE ASSIGNMENT BASED ON 2-DIMENSIONAL PLACEMENT AND HYPERCUBE MAPPING
Authors: LIU S PEDRAM M DESPAIN AM
Citation: S. Liu et al., STATE ASSIGNMENT BASED ON 2-DIMENSIONAL PLACEMENT AND HYPERCUBE MAPPING, Integration, 24(2), 1997, pp. 101-118
CONSTRUCTING MINIMAL SPANNING STEINER TREES WITH BOUNDED PATH-LENGTH/
Authors: OH J PYO I PEDRAM M
Citation: J. Oh et al., CONSTRUCTING MINIMAL SPANNING STEINER TREES WITH BOUNDED PATH-LENGTH/, Integration, 22(1-2), 1997, pp. 137-163
POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS (VOL 3, PG 404, 1995)
Authors: TSUI CY MONTEIRO J PEDRAM M DEVADAS S DESPAIN AM LIN B
Citation: Cy. Tsui et al., POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS (VOL 3, PG 404, 1995), IEEE transactions on very large scale integration (VLSI) systems, 4(4), 1996, pp. 495-495
AN APPROACH FOR MULTILEVEL LOGIC OPTIMIZATION TARGETING LOW-POWER (VOL 15, PG 889, 1996)
Authors: IMAN S PEDRAM M
Citation: S. Iman et M. Pedram, AN APPROACH FOR MULTILEVEL LOGIC OPTIMIZATION TARGETING LOW-POWER (VOL 15, PG 889, 1996), IEEE transactions on computer-aided design of integrated circuits and systems, 15(9), 1996, pp. 1176-1176
AN APPROACH FOR MULTILEVEL LOGIC OPTIMIZATION TARGETING LOW-POWER
Authors: IMAN S PEDRAM M
Citation: S. Iman et M. Pedram, AN APPROACH FOR MULTILEVEL LOGIC OPTIMIZATION TARGETING LOW-POWER, IEEE transactions on computer-aided design of integrated circuits and systems, 15(8), 1996, pp. 889-901
OBDD-BASED FUNCTION DECOMPOSITION - ALGORITHMS AND IMPLEMENTATION
Authors: LAI YT PAN KRR PEDRAM M
Citation: Yt. Lai et al., OBDD-BASED FUNCTION DECOMPOSITION - ALGORITHMS AND IMPLEMENTATION, IEEE transactions on computer-aided design of integrated circuits and systems, 15(8), 1996, pp. 977-990
INTRODUCTION TO THE SPECIAL ISSUE ON LOW-POWER DESIGN
Authors: PEDRAM M FUJITA M
Citation: M. Pedram et M. Fujita, INTRODUCTION TO THE SPECIAL ISSUE ON LOW-POWER DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 15(6), 1996, pp. 569-570
INFORMATION-THEORETIC MEASURES FOR POWER ANALYSIS
Authors: MARCULESCU D MARCULESCU R PEDRAM M
Citation: D. Marculescu et al., INFORMATION-THEORETIC MEASURES FOR POWER ANALYSIS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(6), 1996, pp. 599-610
DIFFERENTIAL EXPRESSION OF THE EXPRESSION SITE-ASSOCIATED GENE-I FAMILY IN AFRICAN TRYPANOSOMES
Authors: MORGAN RW ELSAYED NMA KEPA JK PEDRAM M DONELSON JE
Citation: Rw. Morgan et al., DIFFERENTIAL EXPRESSION OF THE EXPRESSION SITE-ASSOCIATED GENE-I FAMILY IN AFRICAN TRYPANOSOMES, The Journal of biological chemistry, 271(16), 1996, pp. 9771-9777
FORMAL VERIFICATION USING EDGE-VALUED BINARY DECISION DIAGRAMS
Authors: LAI YT PEDRAM M VRUDHULA SBK
Citation: Yt. Lai et al., FORMAL VERIFICATION USING EDGE-VALUED BINARY DECISION DIAGRAMS, I.E.E.E. transactions on computers, 45(2), 1996, pp. 247-255
POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS
Authors: TSUI CY MONTEIRO J PEDRAM M DEVADAS S DESPAIN AM LIN B
Citation: Cy. Tsui et al., POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 3(3), 1995, pp. 404-416
LOW-POWER DESIGN
Authors: HINES J KO U MEIER SE NAPPER S PEDRAM M ROY K
Citation: J. Hines et al., LOW-POWER DESIGN, IEEE design & test of computers, 12(4), 1995, pp. 84-90
COMPUTING THE AREA VERSUS DELAY TRADE-OFF CURVES IN TECHNOLOGY MAPPING
Authors: CHAUDHARY K PEDRAM M
Citation: K. Chaudhary et M. Pedram, COMPUTING THE AREA VERSUS DELAY TRADE-OFF CURVES IN TECHNOLOGY MAPPING, IEEE transactions on computer-aided design of integrated circuits and systems, 14(12), 1995, pp. 1480-1489
THE EFFECT OF THE S14A MUTATION ON THE CONFORMATION AND THERMOSTABILITY OF SACCHAROMYCES-CEREVISIAE G-ACTIN AND ITS INTERACTION WITH ADENINE-NUCLEOTIDES
Authors: CHEN X PENG JM PEDRAM M SWENSON CA RUBENSTEIN PA
Citation: X. Chen et al., THE EFFECT OF THE S14A MUTATION ON THE CONFORMATION AND THERMOSTABILITY OF SACCHAROMYCES-CEREVISIAE G-ACTIN AND ITS INTERACTION WITH ADENINE-NUCLEOTIDES, The Journal of biological chemistry, 270(19), 1995, pp. 11415-11423
POWER CONSCIOUS CAD TOOLS AND METHODOLOGIES - A PERSPECTIVE
Authors: SINGH D RABAEY JM PEDRAM M CATTHOOR F RAJGOPAL S SEHGAL N MOZDZEN TJ
Citation: D. Singh et al., POWER CONSCIOUS CAD TOOLS AND METHODOLOGIES - A PERSPECTIVE, Proceedings of the IEEE, 83(4), 1995, pp. 570-594
Risultati: 1-25 | 26-28