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Results: 1-7 |
Results: 7
A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION, Integration, 24(1), 1997, pp. 37-52
TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS, Electronics Letters, 33(6), 1997, pp. 485-486
REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING
Authors: GIRARD P LANDRAULT G PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING, Electronics Letters, 33(21), 1997, pp. 1752-1754
BIST TEST PATTERN GENERATOR FOR DELAY TESTING
Authors: GIRARD P LANDRAULT C MOREDA V PRAVOSSOUDOVITCH S
Citation: P. Girard et al., BIST TEST PATTERN GENERATOR FOR DELAY TESTING, Electronics Letters, 33(17), 1997, pp. 1429-1431
AN ADVANCED DIAGNOSTIC METHOD FOR DELAY FAULTS IN COMBINATION FAULTY CIRCUITS
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S
Citation: P. Girard et al., AN ADVANCED DIAGNOSTIC METHOD FOR DELAY FAULTS IN COMBINATION FAULTY CIRCUITS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(3), 1995, pp. 277-294
DELAY-FAULT DIAGNOSIS IN SEQUENTIAL-CIRCUITS BASED ON PATH TRACING
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S RODRIGUEZ B
Citation: P. Girard et al., DELAY-FAULT DIAGNOSIS IN SEQUENTIAL-CIRCUITS BASED ON PATH TRACING, Integration, 19(3), 1995, pp. 199-218
DELAY-FAULT PROPAGATION IN SYNCHRONOUS SEQUENTIAL-CIRCUITS
Authors: CAVALLERA P GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S
Citation: P. Cavallera et al., DELAY-FAULT PROPAGATION IN SYNCHRONOUS SEQUENTIAL-CIRCUITS, Electronics Letters, 30(10), 1994, pp. 765-767
Risultati: 1-7 |