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Results:
1-7
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Results: 7
Untitled
Authors:
Prinetto, P Figueras, J
Citation:
P. Prinetto et J. Figueras, Untitled, J ELEC TEST, 17(3-4), 2001, pp. 207-207
Online and off line BIST in IP-core design
Authors:
Benso, A Chiusano, S Di Natale, G Prinetto, P Bodoni, ML
Citation:
A. Benso et al., Online and off line BIST in IP-core design, IEEE DES T, 18(5), 2001, pp. 92-99
A self-repairing execution, unit for microprogrammed processors
Authors:
Benso, A Chiusano, S Prinetto, P
Citation:
A. Benso et al., A self-repairing execution, unit for microprogrammed processors, IEEE MICRO, 21(5), 2001, pp. 16-22
A high-level EDA environment for the automatic insertion of HD-BIST structures
Authors:
Benso, A Cataldo, S Chiusano, S Prinetto, P Zorian, Y
Citation:
A. Benso et al., A high-level EDA environment for the automatic insertion of HD-BIST structures, J ELEC TEST, 16(3), 2000, pp. 179-184
Exploiting behavioral information in gate-level ATPG
Authors:
Chiusano, S Corno, F Prinetto, P
Citation:
S. Chiusano et al., Exploiting behavioral information in gate-level ATPG, J ELEC TEST, 14(1-2), 1999, pp. 141-148
SymFony: A hybrid topological-symbolic ATPG exploiting RT-level information
Authors:
Corno, F Glaser, U Prinetto, P Reorda, MS Vierhaus, HT Violante, M
Citation:
F. Corno et al., SymFony: A hybrid topological-symbolic ATPG exploiting RT-level information, IEEE COMP A, 18(2), 1999, pp. 191-202
Testing embedded memories in telecommunication systems
Authors:
Barbagallo, S Bodoni, ML Benso, A Chiusano, S Prinetto, P
Citation:
S. Barbagallo et al., Testing embedded memories in telecommunication systems, IEEE COMM M, 37(6), 1999, pp. 84-89
Risultati:
1-7
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