Authors: WATANABE Y WONG H KIRIHATA T KATO D DEBROSSE JK HARA T YOSHIDA M MUKAI H QUADER KN NAGAI T POECHMUELLER P PFEFFERL P WORDEMAN MR FUJII S

Citation: Y. Watanabe et al., A 286MM(2) 256 MB DRAM WITH X32 BOTH-ENDS DQ, IEICE transactions on electronics, E79C(7), 1996, pp. 978-985

Authors: WATANABE Y WONG H KIRIHATA T KATO D DEBROSSE JK HARA T YOSHIDA M MUKAI H QUADER KN NAGAI T POECHMUELLER P PFEFFERL P WORDEMAN MR FUJII S

Citation: Y. Watanabe et al., A 286MM(2) 256MB DRAM WITH X32 BOTH-ENDS DQ, IEEE journal of solid-state circuits, 31(4), 1996, pp. 567-574

Authors: QUADER KN FANG P YUE JT KO PK HU CM

Citation: Kn. Quader et al., HOT-CARRIER-RELIABILITY DESIGN RULES FOR TRANSLATING DEVICE DEGRADATION TO CMOS DIGITAL CIRCUIT DEGRADATION, I.E.E.E. transactions on electron devices, 41(5), 1994, pp. 681-691

Authors: QUADER KN MINAMI ER HUANG WJ KO PK HU CM

Citation: Kn. Quader et al., HOT-CARRIER-RELIABILITY DESIGN GUIDELINES FOR CMOS LOGIC-CIRCUITS, IEEE journal of solid-state circuits, 29(3), 1994, pp. 253-262

Authors: QUADER KN LI CC TU R ROSENBAUM E KO PK HU CM

Citation: Kn. Quader et al., A BIDIRECTIONAL NMOSFET CURRENT REDUCTION MODEL FOR SIMULATION OF HOT-CARRIER-INDUCED CIRCUIT DEGRADATION, I.E.E.E. transactions on electron devices, 40(12), 1993, pp. 2245-2254