AAAAAA

   
Results: 1-4 |
Results: 4
DYNAMIC RECONFIGURATION SCHEMES FOR MEGABIT BICMOS SRAMS AND PERFORMANCE EVALUATION
Authors: RAYAPATI VN KAMINSKA B
Citation: Vn. Rayapati et B. Kaminska, DYNAMIC RECONFIGURATION SCHEMES FOR MEGABIT BICMOS SRAMS AND PERFORMANCE EVALUATION, Microelectronics and reliability, 37(5), 1997, pp. 785-794
INTERCONNECT PROPAGATION DELAY MODELING AND VALIDATION FOR THE 16-MB CMOS SRAM CHIP
Authors: RAYAPATI VN KAMINSKA B
Citation: Vn. Rayapati et B. Kaminska, INTERCONNECT PROPAGATION DELAY MODELING AND VALIDATION FOR THE 16-MB CMOS SRAM CHIP, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 19(3), 1996, pp. 605-614
A DYNAMIC RECONFIGURATION SCHEME FOR MEGA BIT STATIC RANDOM-ACCESS MEMORIES
Authors: RAYAPATI VN KAMINSKA B
Citation: Vn. Rayapati et B. Kaminska, A DYNAMIC RECONFIGURATION SCHEME FOR MEGA BIT STATIC RANDOM-ACCESS MEMORIES, Microelectronics and reliability, 34(1), 1994, pp. 107-114
PERFORMANCE ANALYSIS OF MULTILAYER INTERCONNECTIONS FOR MEGABIT STATIC RANDOM-ACCESS MEMORY CHIP
Authors: RAYAPATI VN KAMINSKA B
Citation: Vn. Rayapati et B. Kaminska, PERFORMANCE ANALYSIS OF MULTILAYER INTERCONNECTIONS FOR MEGABIT STATIC RANDOM-ACCESS MEMORY CHIP, IEEE transactions on components, hybrids, and manufacturing technology, 16(5), 1993, pp. 469-477
Risultati: 1-4 |