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Results: 1-10 |
Results: 10
INTERLEAVING BUFFER INSERTION AND TRANSISTOR SIZING INTO A SINGLE OPTIMIZATION
Authors: JIANG YB SAPATNEKAR SS BAMJI C KIM J
Citation: Yb. Jiang et al., INTERLEAVING BUFFER INSERTION AND TRANSISTOR SIZING INTO A SINGLE OPTIMIZATION, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 625-633
AN ALGORITHM FOR SIMULATING POWER GROUND NETWORKS USING PADE APPROXIMANTS AND ITS SYMBOLIC IMPLEMENTATION/
Authors: SHAH JC YOUNIS AA SAPATNEKAR SS HASSOUN MM
Citation: Jc. Shah et al., AN ALGORITHM FOR SIMULATING POWER GROUND NETWORKS USING PADE APPROXIMANTS AND ITS SYMBOLIC IMPLEMENTATION/, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(10), 1998, pp. 1372-1382
MOMENT-BASED TECHNIQUES FOR RLC CLOCK TREE CONSTRUCTION
Authors: LEHTHER D SAPATNEKAR SS
Citation: D. Lehther et Ss. Sapatnekar, MOMENT-BASED TECHNIQUES FOR RLC CLOCK TREE CONSTRUCTION, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(1), 1998, pp. 69-79
SPEEDING-UP PIPELINED CIRCUITS THROUGH A COMBINATION OF GATE SIZING AND CLOCK SKEW OPTIMIZATION
Authors: SATHYAMURTHY H SAPATNEKAR SS FISHBURN JP
Citation: H. Sathyamurthy et al., SPEEDING-UP PIPELINED CIRCUITS THROUGH A COMBINATION OF GATE SIZING AND CLOCK SKEW OPTIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 17(2), 1998, pp. 173-182
OPTIMAL-DESIGN OF MACROCELLS FOR LOW-POWER AND HIGH-SPEED
Authors: SANCHETI PK SAPATNEKAR SS
Citation: Pk. Sancheti et Ss. Sapatnekar, OPTIMAL-DESIGN OF MACROCELLS FOR LOW-POWER AND HIGH-SPEED, IEEE transactions on computer-aided design of integrated circuits and systems, 15(9), 1996, pp. 1160-1166
WIRE SIZING AS A CONVEX-OPTIMIZATION PROBLEM - EXPLORING THE AREA-DELAY TRADEOFF
Authors: SAPATNEKAR SS
Citation: Ss. Sapatnekar, WIRE SIZING AS A CONVEX-OPTIMIZATION PROBLEM - EXPLORING THE AREA-DELAY TRADEOFF, IEEE transactions on computer-aided design of integrated circuits and systems, 15(8), 1996, pp. 1001-1011
UTILIZING THE RETIMING-SKEW EQUIVALENCE IN A PRACTICAL ALGORITHM FOR RETIMING LARGE CIRCUITS
Authors: SAPATNEKAR SS DEOKAR RB
Citation: Ss. Sapatnekar et Rb. Deokar, UTILIZING THE RETIMING-SKEW EQUIVALENCE IN A PRACTICAL ALGORITHM FOR RETIMING LARGE CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(10), 1996, pp. 1237-1248
TIMING AND AREA OPTIMIZATION FOR STANDARD-CELL VLSI CIRCUIT-DESIGN
Authors: CHUANG WT SAPATNEKAR SS HAJJ IN
Citation: Wt. Chuang et al., TIMING AND AREA OPTIMIZATION FOR STANDARD-CELL VLSI CIRCUIT-DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 14(3), 1995, pp. 308-320
CONVEXITY-BASED ALGORITHMS FOR DESIGN CENTERING
Authors: SAPATNEKAR SS VAIDYA PM KANG SM
Citation: Ss. Sapatnekar et al., CONVEXITY-BASED ALGORITHMS FOR DESIGN CENTERING, IEEE transactions on computer-aided design of integrated circuits and systems, 13(12), 1994, pp. 1536-1549
AN EXACT SOLUTION TO THE TRANSISTOR SIZING PROBLEM FOR CMOS CIRCUITS USING CONVEX-OPTIMIZATION
Authors: SAPATNEKAR SS RAO VB VAIDYA PM KANG SM
Citation: Ss. Sapatnekar et al., AN EXACT SOLUTION TO THE TRANSISTOR SIZING PROBLEM FOR CMOS CIRCUITS USING CONVEX-OPTIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 12(11), 1993, pp. 1621-1634
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