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Results: 1-11 |
Results: 11
NEW WRITE ERASE OPERATION TECHNOLOGY FOR FLASH EEPROM CELLS TO IMPROVE THE READ DISTURB CHARACTERISTICS/
Authors: ENDOH T IIZUKA H SHIROTA R MASUOKA F
Citation: T. Endoh et al., NEW WRITE ERASE OPERATION TECHNOLOGY FOR FLASH EEPROM CELLS TO IMPROVE THE READ DISTURB CHARACTERISTICS/, IEICE transactions on electronics, E80C(10), 1997, pp. 1317-1323
A SIDE-WALL TRANSFER-TRANSISTOR CELL (SWATT CELL) FOR HIGHLY RELIABLEMULTILEVEL NAND EEPROMS
Authors: ARITOME S TAKEUCHI Y SATO S WATANABE H SHIMIZU K HEMINK G SHIROTA R
Citation: S. Aritome et al., A SIDE-WALL TRANSFER-TRANSISTOR CELL (SWATT CELL) FOR HIGHLY RELIABLEMULTILEVEL NAND EEPROMS, I.E.E.E. transactions on electron devices, 44(1), 1997, pp. 145-152
A COMPACT ON-CHIP ECC FOR LOW-COST FLASH MEMORIES
Authors: TANZAWA T TANAKA T TAKEUCHI K SHIROTA R ARITOME S WATANABE H KEMINK G SHIMIZU K SATO S TAKEUCKI Y OHUCHI K
Citation: T. Tanzawa et al., A COMPACT ON-CHIP ECC FOR LOW-COST FLASH MEMORIES, IEEE journal of solid-state circuits, 32(5), 1997, pp. 662-669
A NOVEL PROGRAMMING METHOD USING A REVERSE POLARITY PULSE IN FLASH EEPROMS
Authors: IIZUKA H ENDOH T ARITOME S SHIROTA R MASUOKA F
Citation: H. Iizuka et al., A NOVEL PROGRAMMING METHOD USING A REVERSE POLARITY PULSE IN FLASH EEPROMS, IEICE transactions on electronics, E79C(6), 1996, pp. 832-835
THE LOW ELECTRIC-FIELD CONDUCTION MECHANISM OF SILICON-OXIDE SILICON-NITRIDE SILICON-OXIDE INTERPOLY-SI DIELECTRICS
Authors: MARUYAMA T SHIROTA R
Citation: T. Maruyama et R. Shirota, THE LOW ELECTRIC-FIELD CONDUCTION MECHANISM OF SILICON-OXIDE SILICON-NITRIDE SILICON-OXIDE INTERPOLY-SI DIELECTRICS, Journal of applied physics, 78(6), 1995, pp. 3912-3914
AN ADVANCED NAND-STRUCTURE CELL TECHNOLOGY FOR RELIABLE 3.3-V-64 MB ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORIES (EEPROMS)
Authors: ARITOME S HATAKEYAMA I ENDOH T YAMAGUCHI T SHUTO S IIZUKA H MARUYAMA T WATANABE H HEMINK G SAKUI K TANAKA T MOMODOMI M SHIROTA R
Citation: S. Aritome et al., AN ADVANCED NAND-STRUCTURE CELL TECHNOLOGY FOR RELIABLE 3.3-V-64 MB ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORIES (EEPROMS), JPN J A P 1, 33(1B), 1994, pp. 524-528
MODELING OF THE HOLE CURRENT CAUSED BY FOWLER-NORDHEIM TUNNELING THROUGH THIN OXIDES
Authors: HEMINK G ENDOH T SHIROTA R
Citation: G. Hemink et al., MODELING OF THE HOLE CURRENT CAUSED BY FOWLER-NORDHEIM TUNNELING THROUGH THIN OXIDES, JPN J A P 1, 33(1B), 1994, pp. 546-549
DATA RETENTION CHARACTERISTICS OF FLASH MEMORY CELLS AFTER WRITE AND ERASE CYCLING
Authors: ARITOME S SHIROTA R SAKUI K MASUOKA F
Citation: S. Aritome et al., DATA RETENTION CHARACTERISTICS OF FLASH MEMORY CELLS AFTER WRITE AND ERASE CYCLING, IEICE transactions on electronics, E77C(8), 1994, pp. 1287-1295
A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY
Authors: TANAKA T TANAKA Y NAKAMURA H SAKUI K OODAIRA H SHIROTA R OHUCHI K MASUOKA F HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373
A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY
Authors: TANAKA T TANAKA Y NAKAMURA H SAKUI K OODAIRA H SHIROTA R OHUCHI K MASUOKA F HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373
RELIABILITY ISSUES OF FLASH MEMORY CELLS
Authors: ARITOME S SHIROTA R HEMINK G ENDOH T MASUOKA F
Citation: S. Aritome et al., RELIABILITY ISSUES OF FLASH MEMORY CELLS, Proceedings of the IEEE, 81(5), 1993, pp. 776-788
Risultati: 1-11 |