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Results: 1-11 |
Results: 11
Technology mapping for high-performance static CMOS and pass transistor logic designs
Authors: Jiang, YB Sapatnekar, SS Bamji, C
Citation: Yb. Jiang et al., Technology mapping for high-performance static CMOS and pass transistor logic designs, IEEE VLSI, 9(5), 2001, pp. 577-589
Exact and efficient crosstalk estimation
Authors: Kuhlmann, M Sapatnekar, SS
Citation: M. Kuhlmann et Ss. Sapatnekar, Exact and efficient crosstalk estimation, IEEE COMP A, 20(7), 2001, pp. 858-866
Steiner tree optimization for buffers, blockages, and bays
Authors: Alpert, CJ Gandham, G Hu, J Neves, JL Quay, ST Sapatnekar, SS
Citation: Cj. Alpert et al., Steiner tree optimization for buffers, blockages, and bays, IEEE COMP A, 20(4), 2001, pp. 556-562
Power-delay optimizations in gate sizing
Authors: Sapatnekar, SS Chuang, WT
Citation: Ss. Sapatnekar et Wt. Chuang, Power-delay optimizations in gate sizing, ACM T DES A, 5(1), 2000, pp. 98-114
A new class of convex functions for delay modeling and its application to the transistor sizing problem
Authors: Kasamsetty, K Ketkar, M Sapatnekar, SS
Citation: K. Kasamsetty et al., A new class of convex functions for delay modeling and its application to the transistor sizing problem, IEEE COMP A, 19(7), 2000, pp. 779-788
A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing
Authors: Sapatnekar, SS
Citation: Ss. Sapatnekar, A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing, IEEE COMP A, 19(5), 2000, pp. 550-559
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model
Authors: Hu, J Sapatnekar, SS
Citation: J. Hu et Ss. Sapatnekar, Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model, IEEE COMP A, 19(4), 2000, pp. 446-458
Timing-driven partitioning and timing optimization of mixed static-domino implementations
Authors: Zhao, M Sapatnekar, SS
Citation: M. Zhao et Ss. Sapatnekar, Timing-driven partitioning and timing optimization of mixed static-domino implementations, IEEE COMP A, 19(11), 2000, pp. 1322-1336
Optimizing large multiphase level-clocked circuits
Authors: Maheshwari, N Sapatnekar, SS
Citation: N. Maheshwari et Ss. Sapatnekar, Optimizing large multiphase level-clocked circuits, IEEE COMP A, 18(9), 1999, pp. 1249-1264
Non-Hanan routing
Authors: Hou, HB Hu, J Sapatnekar, SS
Citation: Hb. Hou et al., Non-Hanan routing, IEEE COMP A, 18(4), 1999, pp. 436-444
Retiming control logic
Authors: Maheshwari, N Sapatnekar, SS
Citation: N. Maheshwari et Ss. Sapatnekar, Retiming control logic, INTEGRATION, 28(1), 1999, pp. 33-53
Risultati: 1-11 |