AAAAAA

   
Results: 1-9 |
Results: 9
A LONG DATA RETENTION SOI DRAM WITH THE BODY REFRESH FUNCTION
Authors: TOMISHIMA S MORISHITA F TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Tomishima et al., A LONG DATA RETENTION SOI DRAM WITH THE BODY REFRESH FUNCTION, IEICE transactions on electronics, E80C(7), 1997, pp. 899-904
SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES
Authors: KUGE S MORISHITA F TSURUDA T TOMISHIMA S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Kuge et al., SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES, IEICE transactions on electronics, E79C(7), 1996, pp. 997-1002
A BLANKET SOURCE LINE ARCHITECTURE WITH TRIPLE METAL FOR GIGA SCALE MEMORY LSIS
Authors: TOMISHIMA S KUGE S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Tomishima et al., A BLANKET SOURCE LINE ARCHITECTURE WITH TRIPLE METAL FOR GIGA SCALE MEMORY LSIS, IEICE transactions on electronics, E79C(6), 1996, pp. 808-811
SOI-DRAM CIRCUIT TECHNOLOGIES - FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES
Authors: KUGE S MORISHITA F TSURUDA T TOMISHIMA S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Kuge et al., SOI-DRAM CIRCUIT TECHNOLOGIES - FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES, IEEE journal of solid-state circuits, 31(4), 1996, pp. 586-591
LOW-VOLTAGE CIRCUIT-DESIGN TECHNIQUES FOR BATTERY-OPERATED AND OR GIGA-SCALE DRAMS/
Authors: YAMAGATA T TOMISHIMA S TSUKUDE M TSURUDA T HASHIZUME Y ARIMOTO K
Citation: T. Yamagata et al., LOW-VOLTAGE CIRCUIT-DESIGN TECHNIQUES FOR BATTERY-OPERATED AND OR GIGA-SCALE DRAMS/, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1183-1188
A WELL-SYNCHRONIZED SENSING EQUALIZING METHOD FOR SUB-1.0-V OPERATINGADVANCED DRAMS
Authors: OOISHI T ASAKURA M TOMISHIMA S HIDAKA H ARIMOTO K FUJISHIMA K
Citation: T. Ooishi et al., A WELL-SYNCHRONIZED SENSING EQUALIZING METHOD FOR SUB-1.0-V OPERATINGADVANCED DRAMS, IEICE transactions on electronics, E77C(5), 1994, pp. 762-770
A WELL-SYNCHRONIZED SENSING EQUALIZING METHOD FOR SUB-1.0-V OPERATINGADVANCED DRAMS
Authors: OOISHI T ASAKURA M TOMISHIMA S HIDAKA H ARIMOTO K FUJISHIMA K
Citation: T. Ooishi et al., A WELL-SYNCHRONIZED SENSING EQUALIZING METHOD FOR SUB-1.0-V OPERATINGADVANCED DRAMS, IEEE journal of solid-state circuits, 29(4), 1994, pp. 432-440
AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME
Authors: ASAKURA M OOISHI T TSUKUDE M TOMISHIMA S EIMORI T HIDAKA H OHNO Y ARIMOTO K FUJISHIMA K NISHIMURA T YOSHIHARA T
Citation: M. Asakura et al., AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1303-1309
AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME
Authors: ASAKURA M OOISHI T TSUKUDE M TOMISHIMA S EIMORI T HIDAKA H OHNO Y ARIMOTO K FUJISHIMA K NISHIMURA T YOSHIHARA T
Citation: M. Asakura et al., AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1303-1309
Risultati: 1-9 |