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Results:
1-10
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Results: 10
Authors:
Tian, M
Visvanathan, V
Hantgan, J
Kundert, K
Citation: M. Tian et al., Striving for small-signal stability, IEEE CIRC D, 17(1), 2001, pp. 31-41
Authors:
Mandal, P
Visvanathan, V
Citation: P. Mandal et V. Visvanathan, CMOS op-amp sizing using a geometric programming formulation, IEEE COMP A, 20(1), 2001, pp. 22-38
Authors:
Ramanathan, S
Nandy, SK
Visvanathan, V
Citation: S. Ramanathan et al., Reconfigurable filter coprocessor architecture for DSP applications, J VLSI S P, 26(3), 2000, pp. 333-359
Authors:
Mandal, P
Visvanathan, V
Citation: P. Mandal et V. Visvanathan, Self-biasing of folded cascode CMOS op-amps, INT J ELECT, 87(7), 2000, pp. 795-808
Authors:
Ramanathan, S
Visvanathan, V
Nandy, SK
Citation: S. Ramanathan et al., Architectural synthesis of computational engines for subband adaptive filtering, J VLSI S P, 22(3), 1999, pp. 173-195
Authors:
Singhal, K
Visvanathan, V
Citation: K. Singhal et V. Visvanathan, Statistical device models from worst case files and electrical test data, IEEE SEMIC, 12(4), 1999, pp. 470-484
Authors:
Ramanathan, S
Visvanathan, V
Nandy, SK
Citation: S. Ramanathan et al., Synthesis of ASIPs for DSP algorithms, INTEGRATION, 28(1), 1999, pp. 13-32
Authors:
Ramanathan, S
Visvanathan, V
Citation: S. Ramanathan et V. Visvanathan, Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay, INTEGRATION, 27(1), 1999, pp. 1-32
Authors:
Ramanathan, S
Visvanathan, V
Nandy, SK
Citation: S. Ramanathan et al., A computational engine for multirate FIR digital filtering, SIGNAL PROC, 79(2), 1999, pp. 213-222
Authors:
Mandal, P
Visvanathan, V
Citation: P. Mandal et V. Visvanathan, Active biasing of multistage CMOS op-amps for performance enhancement, INT J ELECT, 86(8), 1999, pp. 933-946
Risultati:
1-10
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