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Citation: Ach. Wu et Nd. Dutt, Guest Editorial 11th International Symposium on System-Level Synthesis andDesign (ISSS'98), IEEE VLSI, 8(5), 2000, pp. 469-471

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Citation: Hp. Su et al., A timing-driven soft-macro placement and resynthesis method in interactionwith chip floorplanning, IEEE COMP A, 18(4), 1999, pp. 475-483