Authors:
HAKAMATA H
SAKAGUCHI H
ZHANG CN
SAKASHITA N
SUZUKI H
MIYAZAKI A
TAKEYA M
TAKAHASHI K
KITAMURA N
HORIUCHI S
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Citation: Cn. Zhang et al., OPTIMAL FAULT-TOLERANT DESIGN APPROACH FOR VLSI ARRAY PROCESSORS, IEE proceedings. Computers and digital techniques, 144(1), 1997, pp. 15-21
Citation: Cn. Zhang et al., A BIDIRECTIONAL VECTOR ASSOCIATIVE MEMORY ARCHITECTURE WITH APPLICATION TO NEURAL NETWORKS, Microelectronics, 27(8), 1996, pp. 713-722
Citation: M. Wang et Cn. Zhang, SINGLE NEURON LOCAL RATIONAL ARITHMETIC REVEALED IN PHASE-SPACE OF INPUT CONDUCTANCES, Biophysical journal, 71(5), 1996, pp. 2380-2393
Citation: Cn. Zhang et al., AN EFFICIENT ALGORITHM AND PARALLEL IMPLEMENTATIONS FOR BINARY AND RESIDUE NUMBER-SYSTEMS, Journal of symbolic computation, 15(4), 1993, pp. 451-462
Citation: Zg. Wang et al., SYNTHESIS AND ANTITUMOR ACTIVITIES OF 4-A LKYLSELENYL-4-DEOXY-4'-DEMETHYLEPIPODOPHYLIOTOXIN, Huaxue xuebao, 51(9), 1993, pp. 933-936
Citation: Cn. Zhang et al., A SYSTEMATIC-APPROACH FOR DESIGNING CONCURRENT ERROR-DETECTING SYSTOLIC ARRAYS USING REDUNDANCY, Parallel computing, 19(7), 1993, pp. 745-764
Citation: Hf. Li et al., SPACE-TIME MAPPING, LATENCY OF DATA-FLOW AND CONCURRENT ERROR-DETECTION IN SYSTOLIC ARRAYS, IEE proceedings. Part E. Computers and digital techniques, 140(1), 1993, pp. 33-44