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Results: 126-150/208
Authors:
WENG JP
PARKER AC
Citation: Jp. Weng et Ac. Parker, TAKING THERMAL CONSIDERATIONS INTO ACCOUNT DURING HIGH-LEVEL SYNTHESIS, VLSI design, 5(2), 1997, pp. 183-193
Authors:
WU ACH
Citation: Ach. Wu, DATAPATH OPTIMIZATION USING LAYOUT INFORMATION - AN EMPIRICAL-STUDY, VLSI design, 5(2), 1997, pp. 195-209
Authors:
TSAI FS
HSU YC
Citation: Fs. Tsai et Yc. Hsu, LAYOUT MODELING AND DESIGN SPACE EXPLORATION IN PSS1 SYSTEM, VLSI design, 5(2), 1997, pp. 211-221
Authors:
CHANG KE
CHEN SW
Citation: Ke. Chang et Sw. Chen, AN EFFICIENT AND PAST ALGORITHM FOR ROUTING OVER THE CELLS, VLSI design, 5(1), 1996, pp. 1-10
Authors:
BHATIA D
SHANKAR V
Citation: D. Bhatia et V. Shankar, GREEDY SEGMENTED CHANNEL ROUTER, VLSI design, 5(1), 1996, pp. 11-21
Authors:
GUDMUNDSSON G
NTAFOS S
Citation: G. Gudmundsson et S. Ntafos, A GREEDY ALGORITHM FOR OVER-THE-CELL CHANNEL ROUTING, VLSI design, 5(1), 1996, pp. 23-36
Authors:
SAAB Y
Citation: Y. Saab, A FAST CLUSTERING-BASED MIN-CUT PLACEMENT ALGORITHM WITH SIMULATED-ANNEALING PERFORMANCE, VLSI design, 5(1), 1996, pp. 37-48
Authors:
KAPOOR B
NAIR VSS
Citation: B. Kapoor et Vss. Nair, IMPROVING PATH SENSITIZABILITY OF COMBINATIONAL-CIRCUITS, VLSI design, 5(1), 1996, pp. 49-57
Authors:
ZHU JB
ABDELBARR M
MCCROSKY C
Citation: Jb. Zhu et al., A NEW THEORY FOR TESTABILITY-PRESERVING OPTIMIZATION OF COMBINATIONAL-CIRCUITS, VLSI design, 5(1), 1996, pp. 59-75
Authors:
RAVIKUMAR CP
SAXENA V
Citation: Cp. Ravikumar et V. Saxena, TOGAPS - A TESTABILITY ORIENTED GENETIC ALGORITHM FOR PIPELINE SYNTHESIS, VLSI design, 5(1), 1996, pp. 77-87
Authors:
COMER DT
Citation: Dt. Comer, ZENER ZAP ANTI-FUSE TRIM IN VLSI CIRCUITS, VLSI design, 5(1), 1996, pp. 89-100
Authors:
PEARSON MW
LYONS PJ
APPERLEY MD
Citation: Mw. Pearson et al., HIGH-LEVEL GRAPHICAL ABSTRACTION IN DIGITAL DESIGN, VLSI design, 5(1), 1996, pp. 101-110
Authors:
BHATIA D
Citation: D. Bhatia, FIELD-PROGRAMMABLE GATE ARRAYS, VLSI design, 4(4), 1996, pp. 1-2
Authors:
BROWN S
KHELLAH M
LEMIEUX G
Citation: S. Brown et al., SEGMENTED ROUTING FOR SPEED-PERFORMANCE AND ROUTABILITY IN FIELD-PROGRAMMABLE GATE ARRAYS, VLSI design, 4(4), 1996, pp. 275-291
Authors:
ROY K
GUAN BZ
SECHEN C
Citation: K. Roy et al., A SEA-OF-GATES STYLE FPGA PLACEMENT ALGORITHM, VLSI design, 4(4), 1996, pp. 293-307
Authors:
ROY K
SECHEN C
Citation: K. Roy et C. Sechen, A TIMING-DRIVEN PARTITIONING SYSTEM FOR MULTIPLE FPGAS, VLSI design, 4(4), 1996, pp. 309-328
Authors:
CHEREPACHA D
LEWIS D
Citation: D. Cherepacha et D. Lewis, DP-FPGA - AN FPGA ARCHITECTURE OPTIMIZED FOR DATAPATHS, VLSI design, 4(4), 1996, pp. 329-343
Authors:
RAMAN S
LIU CL
JONES LG
Citation: S. Raman et al., TIMING-CONSTRAINED FPGA PLACEMENT - A FORCE-DIRECTED FORMULATION AND ITS PERFORMANCE EVALUATION, VLSI design, 4(4), 1996, pp. 345-355
Authors:
DAS SR
Citation: Sr. Das, VLSI TESTING - SPECIAL ISSUE, VLSI design, 4(3), 1996, pp. 1-4
Authors:
JONE WB
SHAH N
GLEASON A
DAS SR
Citation: Wb. Jone et al., PGEN - A NOVEL-APPROACH TO SEQUENTIAL-CIRCUIT TEST-GENERATION, VLSI design, 4(3), 1996, pp. 149-165
Authors:
MAJHI AK
JACOB J
PATNAIK LM
Citation: Ak. Majhi et al., A NOVEL PATH DELAY-FAULT SIMULATOR USING BINARY LOGIC, VLSI design, 4(3), 1996, pp. 167-179
Authors:
KIM K
SALUJA KK
Citation: K. Kim et Kk. Saluja, HYSIM - HYBRID FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, VLSI design, 4(3), 1996, pp. 181-197
Authors:
EDIRISOORIYA G
Citation: G. Edirisooriya, CLOSED-FORM ALIASING PROBABILITY FOR Q-ARY SYMMETRICAL ERRORS, VLSI design, 4(3), 1996, pp. 199-205
Authors:
SRINIVAS M
PATNAIK LM
Citation: M. Srinivas et Lm. Patnaik, ON GENERATING OPTIMAL SIGNAL PROBABILITIES FOR RANDOM TESTS - A GENETIC APPROACH, VLSI design, 4(3), 1996, pp. 207-215
Authors:
VANDRIS E
SOBELMAN G
Citation: E. Vandris et G. Sobelman, SWITCH-LEVEL DIFFERENTIAL FAULT SIMULATION OF MOS VLSI CIRCUITS, VLSI design, 4(3), 1996, pp. 217-229