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Authors: KIMURA T NAKAMURA K AIMOTO Y MANABE T YAMASHITA N FUJITA Y OKAZAKI S YAMASHINA M

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Authors: SUGIBAYASHI T NARITAKE I TAKADA H INOUE K YAMAMOTO I MATANO T FUJITA M AIMOTO Y TAKESHIMA T UTSUGI S

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Authors: YAMASHITA N KIMURA T FUJITA Y AIMOTO Y MANABE T OKAZAKI S NAKAMURA K YAMASHINA M

Citation: N. Yamashita et al., A 3.84-GIPS INTEGRATED MEMORY ARRAY PROCESSOR WITH 64 PROCESSING ELEMENTS AND A 2-MB SRAM, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1336-1343

Authors: YAMASHITA N KIMURA T FUJITA Y AIMOTO Y MANABE T OKAZAKI S NAKAMURA K YAMASHINA M

Citation: N. Yamashita et al., A 3.84-GIPS INTEGRATED MEMORY ARRAY PROCESSOR WITH 64 PROCESSING ELEMENTS AND A 2-MB SRAM, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1336-1343

Authors: SUGIBAYASHI T TAKESHIMA T NARITAKE I MATANO T TAKADA H AIMOTO Y FURUTA K FUJITA M SAEKI T SUGAWARA H MUROTANI T KASAI N SHIBAHARA K NAKAJIMA K HADA H HAMADA T AIZAKI N KUNIO T KAKEHASHI E MASUMORI K TANIGAWA T

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